Mahfuzul Islam's personal webpage


Welcome to my website

I am A.K.M. Mahfuzul Islam, known as Mahfuz. Since April of 2015, I am working as a Research Associate at the Institute of Industrial Science, the University of Tokyo.

Education

  • Ph.D. in Informatics, January 2014, Kyoto University, Kyoto, Japan
  • Master in Informatics, March 2011, Kyoto University, Kyoto, Japan
  • Bachelor in Electrical and Electronics Engineering, March 2009, Kyoto University, Kyoto, Japan

Research Area

  • On-chip sensors for variability, temperature, leakage, power
  • Models for performance prediction under the presence of dynamic variations
  • Built-in self-healing techniques
  • Body biasing techniques for energy-efficient LSI operation
  • Low power circuit techniques
  • Large area flexible electronics using organic transistor

Skills

  • Complete ASIC design from RTL to physical layout
  • On-chip sensor design, data processing and parameter extraction
  • On-chip feedback system design including phase detectors and control loop
  • Measurement of LSI chips
  • Simulation at various levels of design hierarchy
  • Strong command of various CAD tools from synopsys, cadence, mentor graphics, etc
  • Scripting using Perl, Ruby, Shell, TCL, etc
  • Design automation

Professional Summary

A passionate and accomplished engineer, researcher and educator with extensive research experience and a background that includes:

  • 5 years experience on developing compact statistical models for static and dynamic variability of CMOS transistors. Expertise range from designing and implementing test structures and on-chip monitor/sensor circuits to data measurement, analysis, and parameter extraction.
  • Mixed-signal design experience. Implemented an AES cipher/decipher module with on-chip performance compensation circuit which consists of sensor circuits, controllers and digital-to-analog converters. The biggest challenge was to implement with standard cell based placement and routing.
  • Experience on technology and design co-optimization. Optimization of supply voltage and threshold voltage under circuit activity, temperature and process variation. Strong background on both process and design technologies.
  • Experience of synthesis, place and route, timing sign-off, and measurement of a media-embedded processor with SRAM and PLL IPs.
  • 3 years experience of working as a student employee at Synthesis Corporation which is a university startup company on system LSI design.
  • Experience of chip tape out in process technology nodes of 65 nm, 45 nm and 28 nm. Have good understanding of both bulk and fully depleted SOI technology and their characteristics.
  • Experience on physical layout and timing characterization of standard cells.
  • Several years of experience on design automation, data processing automation, FPGA prototyping, test automation etc.
  • Experience of leading teams consisting of 8–10 members for multiple chip fabrication projects
  • Developed reconfigurable cell topology and circuit architecture for process, leakage and temperature variation sensing which are highly evaluated for the innovative ideas.
  • Received several awards for outstanding research and conference presentations.