Institute of Industrial Science

The University of Tokyo

TEL: +81-3-5452-6253

FAX: +81-3-5452-6632

E-mail:

- Ph.D. in Information Science and Technology, Osaka University, Japan, March, 2010.
- M.E. in Information Science and Technology, Osaka University, Japan, March, 2008.
- B.E. in Electrical and Electronic Engineering, Kyoto University, Japan, March 2002.

- Ultra-low power (subthreshold) circuit design
- Variation modeling
- Large area electronics with organic transistors

- K. Mori, Y. Okuma, X. Zhang, H. Fuketa, T. Sakurai, and M. Takamiya, "Analog-assisted Digital Low Dropout Regulator with Fast Transient Response and Low Output Ripple," Japanese Journal of Applied Physics, vol.53, no.4S, 04EE22, Mar. 2014. (IOP science)
- H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM," IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, pp. 463-470, Mar. 2014. (IEEE Xplore)
- H. Fuketa, M. Nomura, M. Takamiya, and T. Sakurai, "Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits," IEEE Journal of Solid-State Circuits, vol. 49, no. 2, pp. 536-544, Feb. 2014. (IEEE Xplore)
- H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits," IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1986-1994, Aug. 2013. (IEEE Xplore)
- H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 6, pp. 1175-1179, June 2013. (IEEE Xplore)
- K. Ishida, T.-C. Huang, K. Honda, Y. Shinozuka, H. Fuketa, T. Yokota, U. Zschieschang, H. Klauk, G. Tortissier, T. Sekitani, M. Takamiya, H. Toshiyoshi, T. Someya, and T. Sakurai, "Insole Pedometer With Piezoelectric Energy Harvester and 2V Organic Circuits," IEEE Journal of Solid-State Circuits, vol. 48, no. 1, pp. 255-264, Jan. 2013. (IEEE Xplore)
- R. Takahashi, H. Takata, T. Yasufuku, H. Fuketa, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 59, no. 12, pp. 918-921, Dec 2012. (IEEE Xplore)
- R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron-Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 2791-2795, Dec. 2012. (IEEE Xplore)
- X. Zhang, K. Ishida, H. Fuketa, M. Takamiya, and T. Sakurai, "On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 10, pp. 1876-1880, Oct. 2012. (IEEE Xplore)
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 333-343, Feb. 2012. (IEEE Xplore)
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," IEEE Transactions on Nuclear Science, vol. 58, no. 4, pp. 2097-2102, Aug. 2011. (IEEE Xplore)
- H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, "An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 58, no. 5, pp. 299-303, May 2011. (IEEE Xplore)
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, pp. 1118-1129, Jul. 2010. (IEEE Xplore)
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3094-3102, Dec. 2009.
- K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," IEICE Transactions on Electronics, vol. E92-C, no. 2, pp. 281-285, Feb. 2009.

- H. Fuketa, M. Hamamatsu, T. Yokota, W. Yukita, T. Someya, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "Energy-Autonomous Fever Alarm Armband Integrating Fully Flexible Solar Cells, Piezoelectric Speaker, Temperature Detector, and 12V Organic Complementary FET Circuits," International Solid-State Circuits Conference (ISSCC), Feb. 2015. (to appear)
- H. Fuketa, Y. Momiyama, A. Okamoto, T. Sakata, M. Takamiya, and T. Sakurai, "An 85-mV Input, 50-us Startup Fully Integrated Voltage Multiplier with Passive Clock Boost Using On-Chip Transformers for Energy Harvesting," IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 263-266, Sep. 2014.
- H. Fuketa, K. Yoshioka, K. Fukuda, T. Mori, H. Ota, M. Takamiya, and T. Sakurai, "Design Guidelines of Steep Subthreshold TFET to Minimize Energy of Logic Circuits," International Conference on Solid State Devices and Materials (SSDM), pp. 832-833, Sep. 2014.
- M. Takamiya, H. Fuketa, K. Ishida, T. Yokota, T. Sekitani, T. Someya, and T. Sakurai, "Flexible, Large-Area, and Distributed Organic Electronics Closely Contacted with Skin for Healthcare Applications," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 829-832, Aug. 2014. (invited)
- S. Iguchi, H. Fuketa, T. Sakurai, and M. Takamiya, "92% Start-up Time Reduction by Variation-Tolerant Chirp Injection (CI) and Negative Resistance Booster (NRB) in 39MHz Crystal Oscillator," IEEE Symposium on VLSI Circuits, pp. 189-190, Jun. 2014.
- H. Fuketa, Y. Shinozuka, K. Ishida, M. Takamiya, and T. Sakurai, "On-Chip Buck Converter with Spiral Ferrite Inductor and Reducing IR Drop in 3D Stacked Integration," International Power Electronics Conference (IPEC), pp. 2228-2231, May 2014. (invited)
- T. Yokota, N. Matsuhisa, M. Kaltenbrunner, Y. Inoue, M. Sekino, H. Fuketa, M. Takamiya, T. Sakurai and T. Someya, "Organic Transistor Based Wireless Sensor System with ESD Protection Circuit," Materials Research Society (MRS) Spring Meeting, C6.04, Apr. 2014.
- H. Fuketa, K. Yoshioka, T. Yokota, W. Yukita, M. Koizumi, M. Sekino, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance," International Solid-State Circuits Conference (ISSCC), pp. 490-491, Feb. 2014.
- T. Someya, T. Sekitani, M. Kaltenbrunner, T. Yokota, H. Fuketa, M. Takamiya, and T. Sakurai, "Ultraflexible Organic Devices for Biomedical Applications," International Electron Devices Meeting (IEDM), pp. 8.5.1-8.5.4, Dec. 2013. (invited)
- H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Variation-aware Subthreshold Logic Circuit Design," IEEE International Conference on ASIC (ASICON), pp. 95-98, Oct. 2013. (invited)
- K. Mori, Y. Okuma, X. Zhang, H. Fuketa, K. Ishida, T. Sakurai, and M. Takamiya, "Analog-Assisted Digital Low Dropout Regulator (AADLDO) with 59% Faster Transient Response and 28% Ripple Reduction," International Conference on Solid State Devices and Materials (SSDM), Sep. 2013.
- H. Fuketa, K. Ishida, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "Large-Area and Flexible Sensors with Organic Transistors," International Workshop on Advances in Sensors and Interfaces (IWASI), pp. 87-90, Jun. 2013. (invited)
- S. Iguchi, P. Yeon, H. Fuketa, T. Sakurai, and M. Takamiya, "Zero Phase Difference Capacitance Control (ZPDCC) for Magnetically Resonant Wireless Power Transmission," IEEE MTT-S Wireless Power Transfer Conference (WPTC), May 2013.
- H. Fuketa, Y. Shinozuka, K. Ishida, M. Takamiya, T. Fujii, H. Shimizu, K. Kobayashi, T. Sato, and T. Sakurai, "Efficiency Increase in On-Chip Buck Converter by Introduction of High Permeability Material to Inductor on Interposer," International Conference on Ferrites (ICF), p. 75, Apr. 2013.
- T. Sekitani, T. Yokota, N. Matsuhisa, M. Kaltenbrunner, Y. Inoue, M. Sekino, H. Fuketa, M. Takamiya, T. Sakurai, and T. Someya, "Organic Active Matrix Amplifier System of 1-um Thickness for Multi-channel Surface Electromyogram Measurement," Materials Research Society (MRS) Spring Meeting, SS5.09, Apr. 2013.
- Y. Shinozuka, H. Fuketa, K. Ishida, F. Furuta, K. Osada, K. Takeda, M. Takamiya, and T. Sakurai, "Reducing IR Drop in 3D Integration to Less Than 1/4 Using Buck Converter on Top Die (BCT) Scheme," IEEE International Symposium on Quality Electronic Design (ISQED), pp. 210-215, Mar. 2013.
- H. Fuketa, K. Yoshioka, Y. Shinozuka, K. Ishida, T. Yokota, N. Matsuhisa, Y. Inoue, M. Sekino, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "1um-Thickness 64-Channel Surface Electromyogram Measurement Sheet with 2V Organic Transistors for Prosthetic Hand Control," International Solid-State Circuits Conference (ISSCC), pp. 104-105, Feb. 2013.
- H. Fuketa, M. Nomura, M. Takamiya, and T. Sakurai, "Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits," International Solid-State Circuits Conference (ISSCC), pp. 436-437, Feb. 2013.
- T. Sato, M. Sonehara, H. Kobayashi, F. Sato, K. Hagita, R. Takeda, N. Matsushita, T. Fujii, S. Nakazawa, H. Shimizu, K. Kobayashi, Y. Shinozuka, H. Fuketa, M. Takamiya and T. Sakurai, "Magnetic core power inductor embedded in plastic interposer toward power supply integrated in LSI Package," International Workshop on Power Supply on Chip (PowerSoC), Nov. 2012.
- H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage between NMOS and PMOS in Sub-Threshold Logic Circuits," Custom Integrated Circuits Conference (CICC), 20-3, Sep. 2012.
- H. Fuketa, "Ultra-Low Voltage Logic Design for Extremely Low-Power Circuits," CMOS Emerging Technologies Conference, A6, Jul. 2012. (invited)
- R. Harada, M. Hashimoto, S. Abe, Y. Watanabe, H. Fuketa, and T. Uemura, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," Nuclear and Space Radiation Effects Conference (NSREC), Jul. 2012.
- R. Takahashi, H. Takata, T. Yasufuku, H. Fuketa, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature," International Workshop on Design for Manufacturability and Yield (DFM&Y), Jun. 2012.
- T. Yasufuku, K. Hirairi, Y. Pu, Y.F. Zheng, R. Takahashi, M. Sasaki, H. Fuketa, A. Muramatsu, M. Nomura, H. Shinohara, M. Takamiya, and T. Sakurai, "24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in VDDmin Limited Ultra Low Voltage Logic Circuits," International Symposium on Quality Electronic Design (ISQED), pp. 586-591, Mar. 2012.
- K. Hirairi, Y. Okuma, H. Fuketa, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "13% Power Reduction in 16b Integer Unit in 40nm CMOS by Adaptive Power Supply Voltage Control with Parity-Based Error Prediction and Detection (PEPD) and Fully Integrated Digital LDO," International Solid-State Circuits Conference (ISSCC), pp. 486-487, Feb. 2012.
- K. Ishida, T-C. Huang, K. Honda, Y. Shinozuka, H. Fuketa, T. Yokota, U. Zschieschang, H. Klauk, G. Tortissier, T. Sekitani, M. Takamiya, H. Toshiyoshi, T. Someya, and T. Sakurai, "Insole Pedometer with Piezoelectric Energy Harvester and 2V Organic Digital and Analog Circuits," International Solid-State Circuits Conference (ISSCC), pp. 308-309, Feb. 2012.
- H. Fuketa, S. Iida, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Device-Circuit Interactions in Extremely Low Voltage CMOS Designs," International Electron Devices Meeting (IEDM), pp. 559-562, Dec. 2011. (invited)
- M. Hashimoto and H. Fuketa, "Adaptive Performance Compensation with On-Chip Variation Monitoring," International Midwest Symposium on Circuits and Systems (MWSCAS), Ta1E-4, Aug. 2011. (invited)
- H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "A 12.7-times Energy Efficiency Increase of 16-bit Integer Unit by Power Supply Voltage (VDD) Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF) and Separated VDD between Flip-Flops and Combinational Logics," International Symposium on Low Power Electronics and Design (ISLPED), pp. 163-168, Aug. 2011.
- T. Yasufuku, S. Iida, H. Fuketa, K. Hirairi, M. Nomura, M. Takamiya, and T. Sakurai, "Investigation of Determinant Factors of Minimum Operating Voltage of Logic Gates in 65-nm CMOS," International Symposium on Low Power Electronics and Design (ISLPED), pp. 21-26, Aug. 2011.
- H. Fuketa, S. Iida, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "A Closed-form Expression for Estimating Minimum Operating Voltage (VDDmin) of CMOS Logic Gates," Design Automation Conference (DAC), pp. 984-989, June 2011.
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM," International Reliability Physics Symposium (IRPS), pp. 213-217, May 2010.
- D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-bit RISC Processor with 4.18pJ/cycle at 0.5V Operation," Symposium on Low-Power and High-Speed Chips (COOL Chips), p. 190, Apr. 2010.
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 361-362, Jan. 2010.
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits," Custom Integrated Circuits Conference (CICC), pp. 215-218, Sept. 2009.
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 266-271, Jan. 2009
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits," International Conference on Computer-Aided Design (ICCAD) Colocated Workshop on Test Structure Design for Variability Characterization, Nov. 2008.
- H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits," International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, Aug. 2008.
- K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability," Great Lakes Symposium on VLSI (GLSVLSI), pp. 387-390, May 2008.
- K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 233-238, Oct. 2007.