Journal Papers
1978:
[1] T.Sakurai, K.Hanihara, H.Yanai, "Numerical Analysis Method for Semiconductor Devices with Merged Structure," Spring Convention of IECE of Japan, p.368, Mar.1978.
1979:
[2] T.Sakurai, H.Yanai, "Numerical Analysis of Merged Semiconductor Devices," Journal of IECE of Japan, vol.J62-C, No.1, p.62, Jan.1979.
1981:
[3] T.Sakurai, T.Sugano, "Theory of Continuously Distributed Trap States at Si-SiO2 Interfaces," Journal of Applied Physics, 52(4), pp.2889-1296, Apr.1981.
1983:
[4] T.Sakurai, K.Tamaru, "Simple Formulas for Two- and Three-Dimensional Capacitances," IEEE Transactions on ED, ED-30, No.2, pp.183-185, Feb.1983.
[5] T.Sakurai, "Approximation of Wiring Delay in MOSFET LSI," IEEE Journal of Solid-State Circuits, SC-18, No.4, pp.418-425, Aug.1983.
1984:
[6] T.Sakurai, J.Matsunaga, M.Isobe, T.Ohtani, K.Sawada, A.Aono, H.Nozawa, T.Iizuka, S.Kohyama, "A Low Power 46ns 256Kbit CMOS SRAM with Dynamic Double Word Line," IEEE Journal of Solid-State Circuits, SC-19, No.5, pp.578-585, Oct.1984.
1985:
[7] T.Sakurai, T.Iizuka, "Gate Electrode RC Delay Effects in VLSIs," IEEE Journal of Solid-State Circuits, SC-20, No.1, pp.290-294, Feb.1985.
[8] T.Sakurai, T.Iizuka, "Gate Electrode RC Delay Effects in VLSIs," IEEE Transactions on ED, ED-32, pp.370-374, Feb.1985.
1986:
[9] T.Sakurai, K.Nogami, M.Kakumu, T.Iizuka, "Hot-Carrier Generation in Submicrometer VLSI Environment," IEEE Jouranal of Solid-State Circuits, SC-21, No.1, pp.187-192, Feb.1986.
[10] K.Nogami, T.Sakurai, K.Sawada, T.Wada, M.Isobe, M.Kakumu, S.Morita, M.Yokogawa, M.Kinugawa, T.Asami, K.Hashimoto, J.Matsunage, H.Nozawa, T.Iizuka, "A 1Mb Virtually Static RAM," IEEE Jouranal of Solid-State Circuits, SC-21, No.5, pp.662-669, Oct.1986.
1988:
[11] K.Sawada, T.Sakurai, K.Nogami, K.Sato, T.Shirotori, M.Kakumu, S.Morita, M.Kinugawa, T.Asami, K.Narita, J.Matsunaga, A.Higuchi, T.Iizuka, "A 30uA Data-Retention Pseudo Static RAM with Virtually Static RAM mode," IEEE Jouranal of Solid-State Circuits, SC-23, No.1, pp.12-19.Feb.1988.
[12] T.Sakurai, "Optimization of CMOS Arbiter and Synchronizer with Sub-micron MOSFETs," IEEE Jouranal of Solid-State Circuits, SC-23, No.4, pp.901-906, Aug.1988.
1990:
[13] T.Sakurai, A.R.Newton, "Alpha-Power Law MOSFET Model and Its Application to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid-State Circuits, Vol.25, No.2, pp.584-594, Apr.1990.
1991:
[14] T.Sakurai, A.R.Newton, "Delay Analysis of Series-Connected MOSFET Circuits," IEEE Journal of Solid-State Circuits, Vol.26, No.2, pp.122-131, Feb.1991.
[15] T.Sakurai, A.R.Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on ED, Vol.38, No.4, pp.887-894, Apr.1991.
[16] H.Hara, T.Sakurai, M.Noda, T.Nagamatsu, K.Seta, H.Momose, Y.Niitsu, H.Miyakawa, Y.Watanabe, "0.5um 2M-Transistor BiPNMOS Channelless Gate Array," IEEE Journal of Solid-State Circuits, Vol.26, No.11, pp.1615-1620, Nov.1991.
1992:
[17] T.Sakurai, B.Lin, A.R.Newton, "Fast Simulated Diffusion: An Optimization Algorithm for Multiminimum Problems and Its Application to MOSFET Model Parameter Extraction," IEEE Transactions on Computer-Aided Design, Vol.11, No.2, pp.228-234, Feb.1992.
[18] T.Sakurai, "A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization," IEEE Journal of Solid-State Circ., SC-27, No.7, pp.1014-1019, Jul.1992.
[19] H.Hara, T.Sakurai, T.Nagamatsu, K.Seta, H.Momose, Y.Niitsu, H.Miyakawa, K.Matsuda, Y.Watanabe, F.Sano, A.Chiba, "0.5um 3.3V BiCMOS Standard Cells with 32kilobyte Cache and Ten-Port Register File," IEEE Journal of Solid-State Circuits, Vol.27, No.11, pp.1579-1584, Nov.1992.
1993:
[20] T.Sakurai, "Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI's," IEEE Transactions on ED, Vol.40, No.1, pp.118-124, Jan.1993.
1994:
[21] Y.Unekawa, T.Kobayashi, T.Shirotori, Y.Fujimoto, T.Shimazawa, K.Nogami, T.Nakao, K.Sawada, M.Matsui, T.Sakurai, M.K.Tang, B.Huffman, "A 110-MHz/1-Mb Synchronous TagRAM", IEEE Journal of Solid-State Circuits, vol.29, pp.403-410, Apr.1994.
[22] M.Matsui, H.Hara, Y.Uetani, L.Kim, T.Nagamatsu, Y.Watanabe, A.Chiba, K.Matsuda, T.Sakurai, "A 200MHz 13 mm2 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme," IEEE Journal of Solid-State Circuits, Vol.29, No.12, pp.1482-1490, Dec.1994.
1995:
[23] T.Kuroda, T.Sakurai, "Overview of Low-Power ULSI Circuit Techniques (Invited)," IEICE Transactions on Electronics, Vol.E78-C, No.4, pp.334-344, Apr.1995.
1996:
[24] H.Hara, M.Matsui, G.Otomo, K.Seta, T.Sakurai, "Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment," IEICE Transactions on Electronics, Vol.E79-C No.6, pp.750-756, Jun.1996.
[25] A.Parameswar, H.Hara, T.Sakurai, "A High-Speed, Low-Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications," IEEE J.of Solid-State Circuits, vol.31, no.6, pp.804-809, Jun.1996.
[26] T.Kuroda, T.Sakurai, "Threshold-Voltage Control Schemes through Substrate-Bias for Low-Power High-Speed CMOS LSI Designs," Journal of VLSI Signal Processors, vol.13, no.2/3, pp.191-201, Aug.1996.
[27] T.Kuroda, T.Fujita, S.Mita, T.Nagamatsu, S.Yoshioka, K.Suzuki, F.Sano, M.Norishima, M.Murota, M.Kako, M.Kinugawa, M.Kakumu, T.Sakurai, "A 0.9-V, 150-MHz 10-mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE Journal of Solid-State Circuits, vol.31, no.11, pp.1770-1779, Nov.1996.
1997:
[28] T.Kuroda, T.Sakurai, "Low-Power Circuit Design Technique for Multimedia CMOS VLSI's (Invited)," IEICE Transactions on Electronics, vol.J80-A, no.5, pp.746-752, May 1997.
1998:
[29] S.Ishiwata, T.Sakurai, "Future Direction of Media Processors (Invited)," IEICE Trans.Electron., Vol.E81-C, No.5, pp.629-635.May 1998.
[30] T.Kuroda, K.Suzuki, S.Mita, T.Fujita, F.Yamane, F.Sano, A.Chiba, Y.Watanabe, K.Matsuda, T.Maeda, T.Sakurai, T.Furuyama, "Variable Supply-Voltage Scheme for low-Power High-Speed CMOS Digital Design," IEEE Journal of Solid-State Circuits, vol.33, No.3, pp.454-462, Mar.1998.
[31] H.Kawaguchi, T.Sakurai, "A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction," IEEE J.of Solid-State Circuits, pp.807-811, May 1998.
[32] 石渡俊一, 桜井貴康, "Future Directions of Media Processors", 電子情報通信学会, 英文論文誌, Feb. 1998.
2000:
[33] T.Sakurai, "Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control (Invited)," IEEE International Symposium on Quality Electronic Design, pp.417-423, Mar.2000.
[34] 桜井貴康, "低電力LSI論文小特集の発行にあたって (Invited)," 電子情報通信学会論文誌, Vol.J83-C, No.6, p.445, Jun.2000
[35] 野瀬浩一, 桜井貴康," マイクロIDDQテストのための電流測定デバイス," 電子情報通信学会論文誌, Vol.J83-C, No.6, pp.516-522, Jun.2000.
[36] K.Nose, T.Sakurai, "Analysis and Future Trend of Short-Circuit Power," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.19, No.9, pp.1023-1030, Sept.2000.
[37] H.Kawaguchi, K.Nose, T.Sakurai, "A Super Cut-off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-by Current," IEEE Journal of Solid-State Circuits, vol.35, no.10, pp.1498-1501, Oct.2000.
[38] T.Kuroda, T.Fujita, F.Hatori, T.Sakurai, "Variable threshold-voltage CMOS technology," IEICE Transactions on Electronics, E83C: (11) pp.1705-1715, Nov.2000.
2001:
[39] Y.Shin, K.Choi, T.Sakurai, "Power-Conscious Scheduling for Real-Time Embedded Systems Design, "An International Journal of Custom-Chip Design, Simulation, and Testing, pp.139-150, 2001.
[40] Y.Shin, T.Sakurai, "Power Distribution Analysis of VLSI Interconnects Using Model Order Reduction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.21, No.6, pp.739-745, Jun.2001.
[41] T.Sakurai, "Superconnect Technology (Invited)," IEICE Transactions on Electronics, pp.1709-1716, Dec.2001.
[42] K.Kanda, K.Nose, H.Kawaguchi, T.Sakurai, "Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's," IEEE Journal of Solid-State Circuits, pp.1559-64, Oct.2001.
2002:
[43] H.Kawaguchi, G.Zhang, S.Lee, Y.Shin, T.Sakurai, "A controller LSI for realizing Vdd-hopping scheme with off-the-shelf processors and its application to MPEG4 system," IEICE Transactions on Electronics, vol.E58-C, no.2, pp.263-271, Feb.2002.
[44] K.Nose, M.Hirabayashi, H.Kawaguchi, S.Lee, T.Sakurai, "VTH-Hopping Scheme to Reduce Subthreshold Leakage for Low-Power Processors," Journal of Solid-State Circuits, pp.413-419, Mar.2002.
[45] K.Nose, M.Hirabayashi, H.Kawaguchi, S.Lee, T.Sakurai, "VTH-Hopping Scheme to Reduce Subthreshold Leakage for Low-Power Processors," IEEE Journal of Solid-State Circuits, vol.37, no.3, pp.413-419, Mar.2002.
[46] Y.Shin, T.Sakurai, "Power distribution analysis of VLSI interconnects using model order reduction," IEEE Transactions on CAD, vol.21, no.6, pp.739-745, Jun.2002.
[47] Seongsoo Lee, Seungjun Lee,, T.Sakurai, "Energy-Constrained VDD/VTH Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems," Journal of Circuits, Systems, and Computers, vol.11, no.6, pp.611-620, Dec.2002.
2003:
[48] H.Im, T.Inukai, H.Gomyo, T.Hiramoto, T.Sakurai, "VTCMOS Characterisitics and Its Optimum Conditions Predicated By a Compact Analytical Model," IEEE Transactionｓ on very large sacale intagration (VLSI) Systems, Vol.11, No.5, pp.755-761, Oct.2003.
[49] Q.Liu, T.Sakurai, T.Hiramoto, "Optimum Device Consideration for Standby Power Reduction SchemeUsing Drain-Induced Barrier Lowering", Japan Journal of Applied Physics, Vol.42, pp.2171-2175, Apr.2003.
2004:
[50] T.Someya, T.Sekitani, S.Iba, Y.Kato, H.Kawaguchi, T.Sakurai, "A large-area, flexible pressure sensor matrix with organic field-effect transistors for artificial skin applications," Proceedings of the National Academy of Sciences of the United States of America(PNAS), vol.101, no.27, pp.9966-9970, Jul.2004.
[51] T.Sakurai, "Perspectives of Low-Power VLSI's (Invited)," IEICE Transactions, Vol.E87-C, No.4, pp.429-437, Apr.2004.
[52] 十山, 三坂, 相坂, 在塚, 内山, 石橋, 川口, 桜井, "CPU消費電力削減のための周波数-電力協調型電力制御方式の設計ルールとフィードバック予測方式による適用",電子情報通信学会論文誌, Vol.J87-D-I, no.4, pp.452-461, Apr.2004.
[53] K.Kanda, S.Hattori, T.Sakurai, "90% write power-saving SRAM using sense-amplifying memory cell," IEEE Journal of Solid-State Circuits, Vol.39, No.6, pp.927-933, Jun.2004.
[54] Jin-Hyeok Choi, Yingxue Xu, Takayasu Sakurai," Statistical Leakage Current Reduction in High-Leakage Environments Using Locality of Block Activation in Time Domain," IEEE Journal of Solid-State Circuits, vol.37, no.9, pp.1497-1503, Sept.2004.
2005:
[55] T.Sekitani, Y.Kato, S.Iba, T.Someya," Bending Effect of Organic Field-Effect Trasistors with Polyimide Gate Dielectric Layers," Japanese Journal of Applied Physics, vol.44, pp.2841-2844, 2005.
[56] T.Sekitani, S.Iba, Y.Kato, Y.Noguchi, T.Someya, T.Sakurai," Ultra-flexible organic field-effect transistors embedded at a neutral strain position," Applied Physics Letters 87, 173502, 2005.
[57] T.Sekitani, S.Iba, T.Sekitani, Y.Kato, T.Someya, T.Sakurai, "Suppression of DC bias stress-induced degradation of organic field-effect transistors using postannealing effects," Applied Physics Letters 87, 073505, 2005.
[58] S.Iba, T.Sekitani, Y.Kato, T.Someya, H.Kawaguchi, M.Takamiya, T.Sakurai, S.Takagi, "Control of threshold voltage of organic field-effect transistors with double-gate structures," Applied Physics Letters 87, 023509, 2005.
[59] T.Sekitani, Y.Kato, S.Iba, H.Shinaoka, T.Someya, T.Sakurai, S.Takagi, Bending experiment on pentacene field-effect transistors on plastic films, Applied Physics Letters vol.86, 073511, Feb.2005.
[60] H.Kawaguchi, Y.Shin, T.Sakurai, "uITRON-LP: Power-Conscious Real-Time OS Based on Cooperative Voltage Scaling for Multimedia Applications," IEEE Transactions on Multimedia, vol.7, no.1, pp.67-74, Feb.2005.
[61] H.Kawaguchi, T.Someya, T.Sekitani, T.Sakurai, "Cut-and-Paste Customization of Organic FET Integrated Circuits and Its Application to Electronic Artificial Skin," IEEE Journal of Solid-State Circuits, vol.40, no.1, pp.177-185, Jan.2005.
[62] T.Someya, Y.Kato, T.Sekitani, S.Iba, Y.Noguchi, Y.Murase, H.Kawaguchi, T.Sakurai," Conformable, flexible, large-area networks of pressure and thermal sensors with organic transistor active matrixes," Proceedings of the National Academy of Sciences of the United States of America, Vol.102, Issue35, pp.12321-12325, Aug.2005.
[63] T.Someya, Y.Kato, S.Iba, Y.Noguchi, T.Sekitani, H.Kawaguchi, T.Sakurai, "Integration of organic FETs With Organic Photodiodes for a Large Area, Flwxible and Lightweight Sheet Image Scanners," IEEE Transactions on Electron Devices, vol.52, Issue 11, pp.2502-2511, Nov.2005.
2006:
[64] N.Miura, D.Mizoguchi, M.Inoue, T.Sakurai, aT.Kuroda, "A 195-Gb/s 1.2-W Inductive Inter-Chip Wireless Superconnect for 3-D-Stacked System in a Package," IEEE Journal of Solid-State Circuits (JSSC), Vol.41, No.1, pp.23-34, Jan.2006.
[65] T.Someya, T.Sekitani, S.Iba, Y.Kato, T.Sakurai, H.Kawaguchi, "Organic transistor integrated circuits for large-area sensors," MOLECULAR CRYSTALS AND LIQUID CRYSTALS, 444, pp.13-22, 2006.
[66] D.D.Antono, K.Inagaki, H.Kawaguchi, T.Sakurai, "Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.12, pp.3569-3578, 2006.
[67] S.Iba, Y.Kato, T.Sekitani, H.Kawaguchi, T.Sakurai, T.Someya, "Use of laser drilling in the manufacture of organic inverter circuits," Analytical and Bioanalytical Chemistry, Vol.384, No.2, pp.374-377, Jan.2006.
[68] Y.Kato, T.Sekitani, M.Takamiya, M.Doi, K.Asaka, T.Sakurai, T.Someya, "Sheet-type Braille displays by integrating organic field-effect transistors and polymeric actuators," IEEE Transactions on Electron Devices, 2006-J3, Feb.2006.
[69] C.Q.Tran, H.Kawaguchi,T.Sakurai, "Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping," IEICE Transactions on Electronics, Vol.E89-C, No.3, pp.280-286, Mar.2006.
[70] D.D.Antono, K.Inagaki, H.Kawaguchi, T.Sakurai, "Trends of On-Chip Interconnects in Deep Sub-Micron VLSI," IEICE Transactions on Electronics, Vol.E89-C, No.3, pp.392-394, Mar.2006.
[71] T.Sekitani, T.Someya,, T.Sakurai, "Effects of Annealing on Pentacene Field-Effect Transistors using Polyimide Gate Dielectric Layers," Journal of Applied Physics, Apr.2006.
[72] K.Ishida, K.Kanda, A.Tamtrakarn, H.Kawaguchi,, T.Sakurai, "Managing Subthreshold Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T-Switch (AT-Switch) and Super Cut-off CMOS," IEEE Journal of Solid-State Circuits, 41, 4, pp.859-867, Apr.2006.
[73] K.S.Min, H.D.Choi, H.Y.Choi, H.Kawaguchi, T.Sakurai, "Leakage-Suppressed Clock-Gating Circuit With Zigzag Super Cut-Off CMOS (ZSCCMOS) for Leakage-Dominant Sub70-nm and Sub-1-V-VDD LSIs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14, 4, pp.430-435, Apr.2006.
[74] H.Kawaguchi, S.Iba, Y.Kato, T.Sekitani, T.Someya,, T.Sakurai, "A 3D-Stack Organic Sheet-Type Scanner with Double-Wordline and Double-Bitline Structure," IEEE Sensors Journal, 6.5, pp.1209-1217, May.2006.
[75] K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "VDD-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time," IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, pp. 2382 - 2389, Nov. 2006.
2007:
[76] M.Takamiya, T.Sekitani, Y.Kato, H.Kawaguchi, T.Someya, T.Sakurai, "An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display," IEEE Journal of Solid-State Circuits, Vol 42, No.1, Jan.2007.
[77] T.Sakurai, T.Kuroda," A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link," Vol.42 No.1, Jan.2007.
[78] N.Miura, D.Mizoguchi, M.Inoue, K.Niitsu, Y.Nakagawa, M.Tago, M.Fukaishi, T.Sakurai, T.Kuroda, "A 1 Tb/s 3W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link," IEEE Journal of Solid-State Circuits, Vol.42, No.1, pp.111-122, Jan.2007.
[79] M.Takamiya, T.Sekitani, Y.Kato, H.Kawaguchi, T.Someya, T.Sakurai, "An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display," IEEE Journal of Solid-State Circuits, Vol.42, No.1, pp.93-100, Jan.2007.
[80] N.Miura, T.Sakurai, T.Kuroda, "Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array," IEEE Journal of Solid-State Circuits, Vol.42, No.2, pp.410-421, Feb.2007.
[81] Y.Kato, T.Sekitani, M.akamiya, M.Doi, K.Asaka, T.Sakurai, T.Someya, "Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators," IEEE Transactions on Electron Devices, Vol.54, No.2, pp.202-209, Feb.2007.
[82] Y.Kato, T.Sekitani, M.Takamiya, M.Doi, K.Asaka, T.Sakurai, T.Someya, "Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators," IEEE Transactions on Electron Devices, Vol.54, No.2, pp.202-209, Feb.2007.
[83] Tsuyoshi Sekitani, Makoto Takamiya, Yoshiaki Noguchi, Shintaro Nakano, Yusaku Kato, Takayasu Sakurai, and Takao Someya, "A large-area wireless power-transmission sheet using printed organic transistors and plastic MEMS switches," Nature Materials, Vol.6, pp.413-417, Apr.2007.
[84] Fayez Robert Saliba, Hiroshi Kawaguchi, and Takayasu Sakurai, "A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's," IEICE Transactions on Electronics, Vol.E90-C, No.4, pp.743-748, Apr.2007.
[85] Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, and Takayasu Sakurai, "An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors," IEICE Transactions on Electronics, Vol.E90-C, No.4, pp.786-792, Apr.2007.
[86] Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, and Tadahiro Kuroda, "Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link," IEICE Transactions on Electronics, Vol.E90-C, No.4, pp.829-835, Apr.2007.
[87] K.Onizuka, K.Inagaki, H.Kawaguchi, M.Takamiya, T.Sakurai, "Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs," IEEE Journal of Solid-State Circuits, Vol.42, No.11, pp.2404-2409, Nov.2007.
[88] T.Sakurai, T.Someya, "Wireless Power Transmission Sheet," Ouyou Butsuri, Vol.76, No.10, pp.1159-1163, Oct.2007.
[89] Hiroshi Kawaguchi, Danardono Dwi Antono, and Takayasu Sakurai, "Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines," IEICE Transactions on Electronics, Vol.E90-A, No.12, pp.2669-2681, Nov.2007.
2008:
[90] N.Miura, H.Ishikuro, K.Niitsu, T.Sakurai, T.Kuroda, "A 0.14pJ/b Inductive-Coupling Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE Journal of Solid-State Circuits, vol.43, no.1, pp.285-291, Jan.2008.
[91] D. Levacq, M. Takamiya, and T. Sakurai, "Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time," IEEE Journal of Solid-State Circuits, Vol. 43, No. 11, pp. 2390 - 2395, Nov. 2008.
2009:
[92] M.Takamiya, T.Sakurai, "Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering," IPSJ Transactions on System LSI Design Methodology, Vol.2, pp.18 - 29, Feb.2009.(Invited)
[93] N.Miura, Y.Kohama, Y.Sugimori, H.Ishikuro, T.Sakurai, T.Kuroda, "A High-Speed Inductive-Coupling Link with Burst Transmission," IEEE Journal of Solid-State Circuits (Journal of Solid-State Circuits), vol.44, no.3, pp.947-955, Mar.2009.
[94] Y.Nakamura, M.Takamiya, T.Sakurai, "An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise," IEICE Transactions on Electronics, E92-C, No.4, pp.468-472, Apr.2009.
[95] T.Sekitani, K.Zaitsu, Y.Noguchi, K.Ishibe, M.Takamiya, T.Sakurai, T.Someya, "Printed Nonvolatile Memory for a Sheet-Type Communication System," IEEE Transactions on Electron Devices, Vol.56, No.5, pp.1027-1035, May 2009.
[96] L.Liu, Y.Miyamoto, Z.Zhou, K.Sakaida, J.Ryu, K.Ishida, M.Takamiya, T.Sakurai, "A 100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS," IEICE Transactions on Electronics, E92-C, No.6, pp.769-776, Jun.2009.
[97] 桜井貴康, 黒田忠広, 道関隆国, "CMOS LSI低電力回路技術の先駆的開発と実用化," 電子情報通信学会誌, Vol.92, N0.7, pp.506-507, Jul.2009.
[98] G.-S.Kim, M.Takamiya, T.Sakurai, "A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems, "IEEE Transactions on Circuits and Systems―II: Express Briefs, Vol.56, No.9, pp.709 - 713, Sept.2009.
[99] L.Liu, M.Takamiya, T.Sekitani, Y.Noguchi, S.Nakano, K.Zaitsu, T.Kuroda, T.Someya, T.Sakurai, "A 107-pJ/bit 100-kb/s 0.18-um Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet," IEEE Transactions on Circuits and Systems―I: Regular Papers, Vol.56, No.11, pp.2511-2518, Nov.2009.
[100] T.Sekitani, T.Yokota, U.Zschieschang, H.Klauk, S.Bauer, K.Takeuchi, M.Takamiya, T.Sakurai, T.Someya, "Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays," Science, Vol.326, pp.1516 - 1519, Dec.2009.
2010:
[101] K.Ishida, N.Masunaga, Z.Zhou, T.Yasufuku, T.Sekitani, U.Zschieschang, H.Klauk, M.Takamiya, T.Someya, T.Sakurai, "Stretchable EMI Measurement Sheet With 8 X 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 um Silicon CMOS LSIs for Electric and Magnetic Field Detection," IEEE Journal of Solid-State Circuits, Vol.45, No.1, pp.249-259, Jan.2010.
[102] T.Yasufuku, T.Niiyama, Z.Piao, K.Ishida, M.Murakata, M.Takamiya, T.Sakurai, "Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits, "IEICE Transactions on Electronics, E93-C, No.3, pp.332-339, Mar.2010.
[103] T.Yasufuku, K.Ishida, S.Miyamoto, H.Nakai, M.Takamiya, T.Sakurai, "Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories, "IEICE Transactions on Electronics, E93-C, No.3, pp.317-323, Mar.2010.
[104] Y.Kato, T.Sekitani, Y.Noguchi, T.Yokota, M.Takamiya, T.Sakurai and T, Someya, "Large-Area Flexible Ultrasonic Imaging System With an Organic Transistor Active Matrix," IEEE Transactions on Electron Devices, Vol.57, No.5, pp.995 - 1002, May 2010.
[105] L.Liu, Z.Zhou, T.Sakurai, M.Takamiya, "A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS," IEICE Transactions on Electronics, E93-C, No.6, pp.796-802, Jun.2010.
[106] 高宮真, 篠原尋史, 桜井貴康, "極低電圧動作による低エネルギーLSI," 電子情報通信学会誌, 93巻, 11号, pp.943-947, Nov.2010.
2011:
[107] K. Ishida, N. Masunaga, R. Takahashi, T. Sekitani, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "User Customizable Logic Paper (UCLP) with Sea-of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects," IEEE Journal of Solid-State Circuits, Vol.46, No.1, pp. 285-292, Jan. 2011.
[108] K. Johguchi, T. Hatanaka, K. Ishida, T. Yasufuku, M. Takamiya, T. Sakurai, and K. Takeuchi, "Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package," IEEE Transaction on Components, Packaging and Manufacturing Technology, Vol.1, No.2, pp. 269-277, Feb. 2011.
[109] P. -H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications," IEICE Transaction on Electronics, E94-C, No.4, pp.598-604, Apr. 2011.
[110] T. Yokota, T. Nakagawa, T. Sekitani, Y. Noguchi, K. Fukuda, U. Zschieschang, H. Klauk, K. Takeuchi, M. Takamiya, T. Sakurai, and T. Someya, "Control of Threshold Voltage in Low-Voltage Organic Complementary Inverter Circuits with Floating Gate Structures," Applied. Physics. Letters, 98, 193302, May 2011.
[111] Y.Pu, X.Zhang, K.Ikeuchi, A.Muramatsu, A.Kawasumi, M.Takamiya, M.Nomura, H.Shinohara, T.Sakurai, "Post‐Silicon Clock Deskew Employing Hot‐Carrier‐Injection Trimming with On‐chip Skew Monitoring and Auto‐Stressing Scheme for Sub/NearThreshold Digital Circuits," IEEE Transactions on Circuits and Systems II (TCASII), Vol.58, No.5, pp.294-298, May 2011.
[112] L. Liu, T. Sakurai, and M. Takamiya, "A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power-and Area-Efficient PLL for Impulse Radio UWB Receiver," IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp. 1349-1359, June 2011.
[113] K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD," IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp. 1478-1487, June 2011.
[114] Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P. -H. Chen, K. Watanabe, M. Takamiya, and T. Sakurai, "0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS," IEICE Transaction on Electronics, E94-C, No.6, pp. 938-944, June 2011.
[115] X.Zhang, Y.Pu, K.Ishida, Y.Ryu, Y.Okuma, P.H.Chen, K.Watanabe, T.Sakurai, M.Takamiya, "A Variable Output Voltage Switched‐Capacitor DC‐DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage," IEICE Transactions on Electronics, E94-C, No.6, pp. 953-959, June 2011.
[116] L. Liu, T. Sakurai. and M. Takamiya, "0.6V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver," IEICE Transaction on Electronics, E94-C, No.6, pp. 985-991, June 2011.
[117] K. Ikeuchi, H. Kusamitsu, M. Daito, G. -S. Kim, M. Takamiya, and T. Sakurai, "1 Gb/s, 50um X 50um Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling," IEICE Transaction on Electronics, E94-C, No.6, pp. 992-998, June 2011.
[118] T.Yasufuku, Y.Nakamura, Z.Piao, M.Takamiya, T.Sakurai, "Tester-Friendly All Digital Circuits to Measure Dependence of Within-Die Delay Variations on Power Supply Voltage Down to 0.4V," IEICE Transactions on Electronics, Vol.E94-C, No.6, pp.1072-1075, Jun.2011.
[119] M. Daito, Y. Nakata, S. Sasaki, H. Gomyo, H. Kusamitsu, Y. Komoto, K. Iizuka, K. Ikeuchi, G. -S. Kim, M. Takamiya, and T. Sakurai, "Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing," IEEE Journal of Solid-State Circuits, Vol.46, No.10, pp. 2386-2395, Oct. 2011.
2012:
[120] K. Ishida, T. -C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda, M. Takamiya, T. Someya, and T. Sakurai, "A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier," IEEE Journal of Solid-State Circuits, Vol.47, No.1, pp. 301-309, Jan. 2012.
[121] P. -H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and Vth-Tuned Oscillator With Fixed Charge Programming," IEEE Journal of Solid-State Circuits, Vol.47, No.5, pp. 1252-1260, May. 2012.
[122] X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P. -H. Chen, K. Watanabe, T. Sakurai, and M. Takamiya, “A 1-V-Input Switched-Capacitor Voltage Converter with Voltage-Reference-Free Pulse-Density Modulation,” IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol.59, No.6, pp. 361-365, Jun. 2012.
[123] L. Liu, T. Sakurai, and M. Takamiya, "A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network," IEICE Transaction on Electronics, E95-C, No.6, pp. 1035-1041, June 2012.
[124] N. Masunaga, K. Ishida, T. Sakurai, and M. Takamiya, "EMI Camera LSI(EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution," IEICE Transaction on Electronics, E95-C, No.6, pp. 1059-1066, June 2012.
[125] X. Zhang, K. Ishida, H. Fuketa, M. Takamiya, and T. Sakurai, "On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 10, pp. 1876-1880, Oct. 2012.
[126] P. -H. Chen, X. Zhang, K. Ishida, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection," IEEE Journal of Solid-State Circuits, Vol. 47, No. 11, pp. 2554-2562, Nov. 2012.
[127] T. Yokota, T. Sekitani, T. Tokuhara, N. Take, U. Zschieschang, H. Klauk, K. Takimiya, T. -C. Huang, M. Takamiya, T. Sakurai, and T. Someya, "Sheet-Type Flexible Organic Active Matrix Amplifier System Using Pseudo-CMOS Circuits With Floating-Gate Structure," IEEE Transactions on Electron Devices, Vol. 59, No. 12, pp. 3434 - 3441, Dec. 2012.
[128] R. Takahashi, H. Takata, T. Yasufuku, H. Fuketa, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature," IEEE Transactions on Circuits and Systems-II, Express Briefs, Vol.59, No.12, pp. 918-921, Dec. 2012.
[129] K. Mori, H. Lim, S. Iguchi, K. Ishida, M. Takamiya, and T. Sakurai, “Positioning-Free Resonant Wireless Power Transmission Sheet With Staggered Repeater Coil Array (SRCA),” IEEE Antennas and Wireless Propagation Letters, Vol. 11, pp. 1710-1713, Dec. 2012. (Invited)
2013:
[130] K. Ishida, T.-C. Huang, K. Honda, Y. Shinozuka, H. Fuketa, T. Yokota, U. Zschieschang, H. Klauk, G. Tortissier, T. Sekitani, M. Takamiya, H. Toshiyoshi, T. Someya, and T. Sakurai, "Insole Pedometer With Piezoelectric Energy Harvester and 2V Organic Circuits," IEEE Journal of Solid-State Circuits, Vol.48, No.1, pp. 255-264, Jan. 2013.
[131] H. Fuketa, K. Hirairi, T.Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 6, pp. 1175-1179, June 2013.
[132] H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits," IEEE Journal of Solid-State Circuits, Vol. 48, No. 8, pp. 1986-1994, Aug. 2013.
[133] K. Takemura, K. Ishida, Y. Ishii, K. Maeda, M. Takamiya, T. Sakurai, and K. Baba, "Si Interposers with 15-um-thick Spiral Inductors and SrTiO3 Thin Film Capacitors for Novel 3D Stacked Buck Converters," Transactions of The Japan Institute of Electronics Packaging, Vol. 6, No. 1, pp. 78-86, 2013.
2014:
[134] H. Fuketa, M. Nomura, M. Takamiya, and T. Sakurai, "Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits," IEEE Journal of Solid-State Circuits, Vol.49, No.2, pp. 536-544, Feb. 2014.