ũˆäŒĪ‹†Žš ˜_•ķƒŠƒXƒg (1978-2013)

The English version is here.


2014

#2014002
H. Fuketa, K. Yoshioka, T. Yokota, W. Yukita, M. Koizumi, M. Sekino, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance," IEEE International Solid-State Circuits Conference (ISSCC), pp. 490-491, Feb. 2014.
#2014001
H. Fuketa, M. Nomura, M. Takamiya, and T. Sakurai, "Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits," IEEE Journal of Solid-State Circuits, Vol.49, No.2, pp. 536-544, Feb. 2014.

2013

#2013016
X. Zhang, Y. Okuma, P. -H. Chen, K. Ishida, Y. Ryu, K. Watanabe, T. Sakurai, and M. Takamiya, "A 0.6-V Input 94% Peak Efficiency CCM/DCM Digital Buck Converter in 40-nm CMOS with Dual-Mode-Body-Biased Zero-Crossing Detector," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 45-48, Nov. 2013.
#2013015
H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Variation-aware Subthreshold Logic Circuit Design," IEEE International Conference on ASIC (ASICON), pp. 95-98, Oct. 2013. (Invited)
#2013014
K. Mori, Y. Okuma, X. Zhang, H. Fuketa, T. Sakurai, and M. Takamiya, "Analog-Assisted Digital Low Dropout Regulator (AAD-LDO) with 59% Faster Transient Response and 28% Ripple Reduction," International Conference on Solid State Devices and Materials (SSDM), pp. 888-889, Sep. 2013.
#2013013
H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits," IEEE Journal of Solid-State Circuits, Vol. 48, No. 8, pp. 1986-1994, Aug. 2013.
#2013012
H. Fuketa, K. Ishida, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "Large-Area and Flexible Sensors with Organic Transistors," IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), pp. 87-90, June 2013. (Invited)
#2013011
S. Iguchi, A. Saito, Y. Zheng, K. Watanabe, T. Sakurai, and M. Takamiya, "93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage Inverter for Negative Resistance (MINR) in 0.7V, 9.2uW, 39MHz Crystal Oscillator," IEEE Symposium on VLSI Circuits, pp. C142-C143, June 2013.
#2013010
M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, and T. Sakurai, "0.5V Image Processor with 563 GOPS/W SIMD and 32bit CPU Using High Voltage Clock Distribution (HVCD) and Adaptive Frequency Scaling (AFS) with 40nm CMOS," IEEE Symposium on VLSI Circuits, pp. C36-C37, June 2013.
#2013009
H. Fuketa, K. Hirairi, T.Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 6, pp. 1175-1179, June 2013.
#2013008
S. Iguchi, P. Yeon, H. Fuketa, K. Ishida, T. Sakurai, and M. Takamiya, "Zero Phase Difference Capacitance Control (ZPDCC) for Magnetically Resonant Wireless Power Transmission," IEEE Wireless Power Transfer Conference (WPTC), pp. 25-26, May. 2013.
#2013007
H. Fuketa, Y. Shinozuka, K. Ishida, M. Takamiya, T. Fujii, H. Shimizu, K. Kobayashi, T. Sato, and T. Sakurai, "Efficiency Increase in On-Chip Buck Converter by Introduction of High Permeability Material to Inductor on Interposer," International Conference on Ferrites (ICF), p. 75, Apr. 2013.
#2013006
Y. Shinozuka, H. Fuketa, K. Ishida, F. Furuta, K. Osada, K. Takeda, M. Takamiya, and T. Sakurai, "Reducing IR Drop in 3D Integration to Less Than 1/4 Using Buck Converter on Top Die (BCT) Scheme," IEEE International Symposium on Quality Electronic Design (ISQED), pp. 210-215, March 2013.
#2013005
H. Fuketa, M. Nomura, M. Takamiya, T. Sakurai, "Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits," IEEE International Solid-State Circuits Conference (ISSCC), pp. 436-437, Feb. 2013.
#2013004
H. Fuketa, K. Yoshioka, Y. Shinozuka, K. Ishida, T. Yokota, N. Matsuhisa, Y. Inoue, M. Sekino, T. Sekitani, M. Takamiya, T. Someya, T. Sakurai, "1um-Thickness 64-Channel Surface Electromyogram Measurement Sheet with 2V Organic Transistors for Prosthetic Hand Control," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013.
#2013003
S. Iguchi, A. Saito, K. Honda, Y. Zheng, K. Watanabe, T. Sakurai, and M. Takamiya, "315MHz OOK Transceiver with 38-uW Receiver and 36-uW Transmitter in 40-nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 93-94, Jan. 2013.
#2013002
X. Zhang, P. -H. Chen, Y. Ryu, K. Ishida, Y. Okuma, K. Watanabe, T. Sakurai, and M. Takamiya, "A Low Voltage Buck DC-DC Converter Using On-Chip Gate Boost Technique in 40nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 109-110, Jan. 2013.
#2013001
K. Ishida, T.-C. Huang, K. Honda, Y. Shinozuka, H. Fuketa, T. Yokota, U. Zschieschang, H. Klauk, G. Tortissier, T. Sekitani, M. Takamiya, H. Toshiyoshi, T. Someya, and T. Sakurai, "Insole Pedometer With Piezoelectric Energy Harvester and 2V Organic Circuits," IEEE Journal of Solid-State Circuits, Vol.48, No.1, pp. 255-264, Jan. 2013.

2012

#2012013
X. Zhang, P. -H. Chen, Y. Ryu, K. Ishida, Y. Okuma, K. Watanabe, T. Sakurai, and M. Takamiya, "A 0.45-V Input On-Chip Gate Boosted (OGB) Buck Converter in 40-nm CMOS with More Than 90% Efficiency in Load Range from 2ƒĘW to 50ƒĘW," IEEE Symposium on VLSI Circuits, Hawaii, pp. 194-195, June 2012.
[Paper Link]

#2012012
A. Saito, K. Honda, Y. Zheng, S. Iguchi, K. Watanabe, T. Sakurai, and M. Takamiya, "An All 0.5V, 1Mbps, 315MHz OOK Transceiver with 38-ƒĘW Carrier-Frequency-Free Intermittent Sampling Receiver and 52-ƒĘW Class-F Transmitter in 40-nm CMOS," IEEE Symposium on VLSI Circuits, Hawaii, pp. 38-39, June 2012.
[Paper Link]

#2012011
N. Masunaga, K. Ishida, T. Sakurai, and M. Takamiya, "EMI Camera LSI(EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution," IEICE Transaction on Electronics, E95-C, No.6, pp. 1059-1066, June 2012.
[Paper Link]

#2012010
L. Liu, T. Sakurai, and M. Takamiya, "A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network," IEICE Transaction on Electronics, E95-C, No.6, pp. 1035-1041, June 2012.
[Paper Link]

#2012009
H. Lim, K. Ishida, M. Takamiya, and T. Sakurai, "Positioning-Free Magnetically Resonant Wireless Power Transmission Board with Staggered Repeater Coil Array (SRCA)," IEEE MTT-S International Microwave Workshop Series on Innovative Wireless Power Transmission: Technologies, Systems, and Applications (IMWS-IWPT), Kyoto, pp. 93-96, May 2012.
[Paper Link]

#2012008
P. -H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and Vth-Tuned Oscillator With Fixed Charge Programming," IEEE Journal of Solid-State Circuits, Vol.47, No.5, pp. 1252-1260, May. 2012.
[Paper Link]

#2010007
‰„@•―‰F, ˆäŒûr‘ū, ’@”G, Î“cŒõˆę, ũˆä‹MN, ‚‹{@^, "ŽóM“d—Í40mW‚ĖŽĨ‹C‹Ī–ÂŒ^–ģü“d—Í‘—ŽóMLSI‚ĖÝŒv‚Æ•]‰ŋ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCC-12-68C‰ŠŽRC2012”N3ŒŽ.
#2012007
ˆäŒûr‘ū, ꎓĄ@ŧ, “n•Ó˜a‹I, ũˆä‹MN, ‚‹{@^, "315MHz’áo—ÍF‹‰ƒpƒ[ƒAƒ“ƒv‚É‚Ļ‚Ŋ‚éƒfƒ…ƒAƒ‹“dŒđ“dˆģ‚É‚æ‚鍂Œø—Ķ‰ŧ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCC-12-65C‰ŠŽRC2012”N3ŒŽ.
#2012006
T. Yasufuku, K. Hirairi, Y. Pu, Y. -F. Zheng, R. Takahashi, M. Sasaki, H. Fuketa, A. Muramatsu, M. Nomura, F. Shinohara, M. Takamiya, and T. Sakurai, "24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in VDDmin Limited Ultra Low Voltage Logic Circuits," IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, pp. 586-591, March 2012.
[Paper Link]

#2012005
K. Hirairi, Y. Okuma, H. Fuketa, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "13% Power Reduction in 16b Integer Unit in 40nm CMOS by Adaptive Power Supply Voltage Control with Parity-Based Error Prediction and Detection (PEPD) and Fully Integrated Digital LDO," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 486-487, Feb. 2012.
[Paper Link]

#2012004
K. Ishida, T. -C. Huang, K. Honda, Y. Shinozuka, H. Fuketa, T. Yokota, U. Zschieschang, H. Klauk, G. Tortissier, T. Sekitani, M. Takamiya, H. Toshiyoshi, T. Someya, and T. Sakurai, "Insole Pedometer With Piezoelectric Energy Harvester and 2V Organic Digital and Analog Circuits," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 308-309, Feb. 2012.
[Paper Link]

#2012003
K. Ikeuchi, M. Takamiya, and T. Sakurai, "Through Silicon Capacitive Coupling (TSCC) Interface for 3D Stacked Dies," IEEE International Conference on 3D System Integration (3D IC), P-2-5, Osaka, Feb. 2012.
[Paper Link]

#2012002
P. -H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 120-mV Input, Fully Integrated Dual-Mode Charge Pump in 65-nm CMOS for Thermoelectric Energy Harvester," Asia-South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, pp. 469-470, Jan. 2012. (Best Design Award in University LSI Design Contest ‚ðŽóÜ)
[Paper Link]

#2012001
K. Ishida, T. -C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda, M. Takamiya, T. Someya, and T. Sakurai, "A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier," IEEE Journal of Solid-State Circuits, Vol.47, No.1, pp. 301-309, Jan. 2012.
[Paper Link]

2011

#2011046
T. -C. Huang, K. Ishida, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "A Floating-Gate OTFT-Driven AMOLED Pixel Circuit for Variation and Degradation Compensation in Large-Sized Flexible Displays," International Display Workshop (IDW), Nagoya, Japan, pp. 1643-1646, Dec. 2011. (Invited)
[Paper Link]

#2011045
H. Fuketa, T. Yasufuku, S. Iida, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Device-Circuit Interactions in Extremely Low Voltage CMOS Designs," IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, pp. 559-562, Dec. 2011. (Invited)
[Paper Link]

#2011044
T. Yokota, T. Sekitani, T. Tokuhara, U. Zschieschang, H. Klauk, T.-C. Huang, M. Takamiya, T. Sakurai, and T. Someya, "Sheet-type Organic Active Matrix Amplifier System Using Vth-Tunable, Pseudo-CMOS Circuits with Floating-gate Structure," IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, pp. 335-338, Dec. 2011.
#2011043
P. -H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 80-mV Input, Fast Startup Dual-Mode Boost Converter with Charge-Pumped Pulse Generator for Energy Harvesting," IEEE Asian Solid-State Circuits Conference (A-SSCC), Jeju, Korea, pp. 33-36, Nov. 2011.
[Paper Link]

#2011042
—Ŧ@—ĮŸC‘åŒFN‰îCÎ“cŒõˆęC’Ģ@MC’@”GC“n•Ó˜a‹IC‚‹{@^Cũˆä‹MN, "0.5V“ü—́AŒø—Ķ96%‚ĖƒQ[ƒgƒu[ƒXƒg•ûŽŪƒ`ƒƒ[ƒWƒ|ƒ“ƒv‰ņ˜H‚ĖŽĀØ," “d‹CŠw‰ïC“dŽq‰ņ˜HŒĪ‹†‰ïC“d‹CŠw‰ïŒĪ‹†‰ïŽ‘—ŋCECT-11-69Cpp. 11-14C’·čC2011”N10ŒŽ.
2011 #2011041
M. Daito, Y. Nakata, S. Sasaki, H. Gomyo, H. Kusamitsu, Y. Komoto, K. Iizuka, K. Ikeuchi, G. -S. Kim, M. Takamiya, and T. Sakurai, "Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing," IEEE Journal of Solid-State Circuits, Vol.46, No.10, pp. 2386-2395, Oct. 2011.
[Paper Link]

#2011040
ˆĀ•Ÿ@ģC”Ņ“c@’qCX“c—TŽiC•―“üF“ņC–ė‘šđOC‚‹{@^Cũˆä‹MN, "CMOS˜_—ƒQ[ƒg‚ĖÅ’á‰Â“Ū“dˆģ(VDDmin)‚ĖŒˆ’č—vˆö‚Ė•ŠÍ," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, C-12-17CŽD–yC2011”N9ŒŽ.
#2011039
‰„@•―‰FC’@”GCÎ“cŒõˆęC“‡–{‹gCũˆä‹MNC‚‹{@^, "ŽĨ‹C‹Ī–ÂŒ^–ģü“d—Í“`‘—Œü‚Ŋ“d—Í‘—ŽóM‰ņ˜H‚ĖÝŒv‚ÆŽĀ‘Š," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ïCB-1-11CŽD–yC2011”N9ŒŽ.
#2011038
—Ņ@睍ŠCÎ“cŒõˆęC“‡–{‹gCũˆä‹MNC‚‹{@^, "ŽĨ‹C‹Ī–ÂŒ^–ģü“d—Í“`‘—‚É‚Ļ‚Ŋ‚éˆĘ’u‚ļ‚ę‚ɃƒoƒXƒg‚Č‘—MƒRƒCƒ‹ƒAƒŒƒC‚Æ2”{ŒaŽóMƒRƒCƒ‹‚Ė’ņˆÄ‚ÆŽĀØ," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ïCB-1-10CŽD–yC2011”N9ŒŽ.
#2011037
A. Muramatsu, T. Yasufuku, M. Nomura, M. Takamiya, H. Shinohara, and T. Sakurai, "12% Power Reduction by Within-Functional-Block Fine-Grained Adaptive Dual Supply Voltage Control in Logic Circuits with 42 Voltage Domains," 37th European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland, pp. 191-194, Sep. 2011.
[Paper Link]

#2011036
X“c—TŽiC•―“üF“ņCˆĀ•Ÿ@ģC‚‹{@^C–ė‘š@đOCŽÂŒīqŽjCũˆä‹MN, "’á“dˆģ“Ūė‰Â”\‚ČƒRƒ“ƒeƒ“ƒVƒ‡ƒ“ƒŒƒXEƒtƒŠƒbƒvƒtƒƒbƒv‚Æ2Ží‚Ė“dŒđ“dˆģ‚É‚æ‚éŪ”‰‰ŽZ‰ņ˜H‚ĖƒGƒlƒ‹ƒM[Œø—ĶŒüã‚ĖŽĀØ," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņCICD2011-63Cpp. 127-132C•xŽRC2011”N8ŒŽ.
#2011035
–{“cŒ’‘ū˜YC’r“āŽ”VC–ė‘šđOC‚‹{@^Cũˆä‹MN, "ŽĐ“Ū‘I‘ð“d‰Ũ’“ü‚ð—p‚Ē‚―CMOSƒƒWƒbƒN‰ņ˜H‚ĖÅ’á‰Â“Ū“dˆģ(VDDmin)‚Ė’áŒļ," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņCICD2011-62Cpp. 121-126C•xŽRC2011”N8ŒŽ.
#2011034
‚‹{@^CÎ“cŒõˆęCX“c—TŽiC–ė‘šđOCŽÂŒīqŽjCũˆä‹MN, "ƒGƒiƒW[ƒn[ƒxƒXƒg‚ð—p‚Ē‚―–ģüƒZƒ“ƒTƒm[ƒh‚É“K—p‰Â”\‚Č0.5V‹É’á“d—͉ņ˜H‹Zp," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņCICD2011-56Cpp. 87-92C•xŽRC2011”N8ŒŽ. (Invited)
#2011033
K. Ishida, T. -C. Huang, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, " Large-Area Flexible Electronics with Organic Transistors," IEEE International Midwest Symposium on Circuits and Systems, Seoul, Korea, pp. 1-4, Aug. 2011. (Invited)
[Paper Link]

#2011032
K. Honda, K. Ikeuchi, M. Nomura, M. Takamiya, and T. Sakurai, "Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection," International Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, pp. 175-180, Aug. 2011.
[Paper Link]

#2011031
H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "12.7-times Energy Efficiency Increase of 16-bit Integer Unit by Power Supply Voltage (VDD) Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF) and Separated VDD between Flip-Flops and Combinational Logics," International Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, pp. 163-168, Aug. 2011.
[Paper Link]

#2011030
T. Yasufuku, S. Iida, H. Fuketa, K. Hirairi, M. Nomura, M. Takamiya, and T. Sakurai, " Investigation of Determinant Factors of Minimum Operating Voltage of Logic Gates in 65-nm CMOS," International Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, pp. 21-26, Aug. 2011.
[Paper Link]

#2011029
Î“cŒõˆęC‰Đ@ûj–õC–{“cŒ’‘ū˜YCŠÖ’J@‹BC’†“‡G‰ĀC‘O“c”ŽŒČC‚‹{@^Cõ’J—ē•vCũˆä‹MN, "—L‹@CMOS‰ņ˜H‚ð—p‚Ē‚―100V ACÏŽZ“d—ÍŒv," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņCICD2011-25Cpp. 57-62CL“‡C2011”N7ŒŽ.
#2011028
X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P. -H. Chen, K. Watanabe, T. Sakurai, and M. Takamiya, "A Voltage-Reference-Free Pulse Density Modulation (VRF-PDM) 1-V Input Switched-Capacitor 1/2 Voltage Converter with Output Voltage Trimming by Hot Carrier Injection and Periodic Activation Scheme," IEEE Symposium on VLSI Circuits, Kyoto, pp. 280-281, June 2011.
[Paper Link]

#2011027
L. Liu, T. Sakurai, and M. Takamiya, "315MHz Energy-Efficient Injection-Locked OOK Transmitter and 8.4 uW Power-Gated Receiver Front-End for Wireless Ad Hoc Network in 40nm CMOS," IEEE Symposium on VLSI Circuits, Kyoto, pp. 164-165, June 2011.
[Paper Link]

#2011026
H. Fuketa, S. Iida, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "A Closed-Form Expression for Estimating Minimum Operating Voltage (VDDmin) of CMOS Logic Gates," ACM Design Automation Conference, San Diego, USA, pp. 984-989, June 2011.
[Paper Link]

#2011025
T. Yasufuku, Y. Nakamura, Z. Piao, M. Takamiya, and T. Sakurai, "Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout," IEICE Transaction on Electronics, E94-C, No.6, pp. 1072-1075, June 2011.
[Paper Link]

#2011024
K. Ikeuchi, H. Kusamitsu, M. Daito, G. -S. Kim, M. Takamiya, and T. Sakurai, "1 Gb/s, 50um X 50um Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling," IEICE Transaction on Electronics, E94-C, No.6, pp. 992-998, June 2011.
[Paper Link]

#2011023
L. Liu, T. Sakurai. and M. Takamiya, "0.6V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver," IEICE Transaction on Electronics, E94-C, No.6, pp. 985-991, June 2011.
[Paper Link]

#2011022
X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P. -H. Chen, T. Sakurai, and M. Takamiya, "A Variable Output Voltage Switched- Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage," IEICE Transaction on Electronics, E94-C, No.6, pp. 953-959, June 2011.
[Paper Link]

#2011021
Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P. -H. Chen, K. Watanabe, M. Takamiya, and T. Sakurai, "0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS," IEICE Transaction on Electronics, E94-C, No.6, pp. 938-944, June 2011.
[Paper Link]

#2011020
K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD," IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp. 1478-1487, June 2011.
[Paper Link]

#2011019
L. Liu, T. Sakurai, and M. Takamiya, "A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power-and Area-Efficient PLL for Impulse Radio UWB Receiver," IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp. 1349-1359, June 2011.
[Paper Link]

#2011018
‘åŒFN‰îCÎ“cŒõˆęC—Ŧ@—ĮŸC’Ģ@MC’@”GC“n•Ó˜a‹IC‚‹{@^Cũˆä‹MN, "“d—ŽŒø—Ķ98.7% 0.5-V“ü—Í 65nm CMOS ƒfƒWƒ^ƒ‹ƒŒƒMƒ…ƒŒ[ƒ^," “dŽqî•ņ’ʐMŠw‰ïCWÏ‰ņ˜HŒĪ‹†ę–åˆÏˆõ‰ïC‘æ25‰ņƒVƒŠƒRƒ“ƒAƒiƒƒORFŒĪ‹†‰ïCu‰‰”ԍ†3C–k‹ãBC2011”N5ŒŽ.
#2011017
–{“cŒ’‘ū˜YCÎ“cŒõˆęC‰Đ@ûj–õCŠÖ’J@„C’†“‡G‰ĀC‘O“c”Ž–ĪC‚‹{@^Cõ’J—ē•vCũˆä‹MN, "100V ACÏŽZ“d—ÍŒvŒü‚Ŋ‚É100V/20V‚Ė—L‹@ƒfƒWƒ^ƒ‹EƒAƒiƒƒO‰ņ˜H‚ðŽÚ‚ĩ‚―ƒVƒXƒeƒ€EƒIƒ“EƒtƒBƒ‹ƒ€‚ĖŽĀØ," “dŽqî•ņ’ʐMŠw‰ïCLSI‚ƃVƒXƒeƒ€‚Ėƒ[ƒNƒVƒ‡ƒbƒvCƒ|ƒXƒ^[ƒZƒbƒVƒ‡ƒ“ Šwķ•”–å01Cpp. 187-189C–k‹ãBC2011 ”N5ŒŽ. (IEEE SSCS Kansai Chapter Academic Research Award‚ðŽóÜj
#2011016
T. -C. Huang, K. Ishida, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "A Floating-Gate OTFT-Driven AMOLED Pixel Circuit for Variation and Degradation Compensation in Large-Sized Flexible Displays," Society for Information Display (SID) International Symposium, Los Angeles, USA, pp. 149-152, May 2011.
[Paper Link]

#2011015
Y. Pu, X. Zhang, K. Ikeuchi, A. Muramatsu, A. Kawasumi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits," IEEE Transactions on Circuits and Systems-II, Vol. 58, No. 5, pp. 294-298, May 2011.
[Paper Link]

#2011014
T. Yokota, T. Nakagawa, T. Sekitani, Y. Noguchi, K. Fukuda, U. Zschieschang, H. Klauk, K. Takeuchi, M. Takamiya, T. Sakurai, and T. Someya, "Control of Threshold Voltage in Low-Voltage Organic Complementary Inverter Circuits with Floating Gate Structures," Applied. Physics. Letters, 98, 193302, May 2011.
#2011013
P. -H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications," IEICE Transaction on Electronics, E94-C, No.4, pp.598-604, Apr. 2011.
[Paper Link]

#2011012
‚‹{@^CˆĀ•Ÿ@ģCX“c—TŽiCÎ“cŒõˆęCũˆä‹MN, "‹É’á“dˆģ“Ūė‚É‚æ‚é’ī’á“d—͉ņ˜HÝŒv‹Zp," 2011”Nt‹G‘æ58‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ïC25p-KC-5C_“ސėC2011”N3ŒŽ. (Invited)
#2011011
P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "0.18-V Input Charge Pump with Forward Body Biasing," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCC-12-58C“Œ‹žC2011”N3ŒŽ.
#2011010
“A@‰_”ōCÄ“Ą@ŧC“n•Ó˜a‹IC‚‹{@^Cũˆä‹MN, "0.35V, 4.1uW, 39MHz, 40nm CMOS…ŧ”­U‰ņ˜H‚ĖŽĀØ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCC-12-50C“Œ‹žC2011”N3ŒŽ.
#2011009
•Ð‰Š’ž”VCˆĀ•Ÿ@ģCX“c—TŽiC•―“üF“ņC‰Đ@ûj–õC‘šž@“āC–ė‘šđOC‚‹{@^CŽÂŒīqŽjCũˆä‹MN, "Å’á‰Â“Ū“dˆģ(VDDmin)‚Ė’á‚ĒƒtƒŠƒbƒvƒtƒƒbƒv‰ņ˜Hƒgƒ|ƒƒW[‚Ė’Tõ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCC-12-33C“Œ‹žC2011”N3ŒŽ.
#2011008
ˆĀ•Ÿ@ģC’†‘šˆĀŒĐC–p@“NC‚‹{@^Cũˆä‹MN, "’á“dŒđ“dˆģ—Ėˆæ‚É‚Ļ‚Ŋ‚éƒ`ƒbƒv“ā’x‰„ŽžŠÔ‚΂į‚‚Ŧ‚Ė‘Š’č," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCC-12-31C“Œ‹žC2011”N3ŒŽ.
#2011007
–{“cŒ’‘ū˜YCÎ“cŒõˆęC‰Đ@ûj–õCŠÖ’J@‹BC‚‹{@^Cõ’J—ē•vCũˆä‹MN, "20V—L‹@CMOSƒIƒyƒAƒ“ƒv‚É‚Ļ‚Ŋ‚éƒtƒ[ƒeƒBƒ“ƒOƒQ[ƒg‚ð—˜—p‚ĩ‚―ƒvƒƒZƒX‚΂į‚‚Ŧ•âģ‹Zp‚Ė’ņˆÄ‚ÆŽĀØ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCC-12-30C“Œ‹žC2011”N3ŒŽ.
#2011006
—Ņ@睍ŠC“‡–{‹gCũˆä‹MNC‚‹{@^, "ŽĨ‹C‹Ī–ÂŒ^–ģü“d—Í“`‘—‚É‚Ļ‚Ŋ‚éˆĘ’u‚ļ‚ę‚ɃƒoƒXƒg‚Č‘—MƒRƒCƒ‹ƒAƒŒ[‚ĖƒI[ƒvƒ“EƒVƒ‡[ƒg§Œä•ûŽŪ‚Ė’ņˆÄ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ïCB-1-6C“Œ‹žC2011”N3ŒŽ.
#2011005
K. Ishida, T. -C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda, M. Takamiya, T. Someya, and T. Sakurai, "100-V AC Power Meter System-on-a-Film (SoF) Integrating 20-V Organic CMOS Digital and Analog Circuits with Floating Gate for Process Variation Compensation and 100-V Organic PMOS Rectifier," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 218-219, Feb. 2011.
[Paper Link]

#2011004
P. -H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 95mV-Startup Step-up Converter with VTH-Tuned Oscillator by Fixed-Charge Programming and Capacitor Pass-On Scheme," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 216-217, Feb. 2011.
[Paper Link]

#2011003
K. Johguchi, T. Hatanaka, K. Ishida, T. Yasufuku, T. Takamiya, T. Sakurai, and K. Takeuchi, "Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package," IEEE Transaction on Components, Packaging and Manufacturing Technology, Vol.1, No.2, pp. 269-277, Feb. 2011.
#2011002
X. Zhang, K. Ishida, M. Takamiya, and T. Sakurai, "An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 109-110, Jan. 2011.
[Paper Link]

#2011001
K. Ishida, N. Masunaga, R. Takahashi, T. Sekitani, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "User Customizable Logic Paper (UCLP) with Sea-of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects," IEEE Journal of Solid-State Circuits, Vol.46, No.1, pp. 285-292, Jan. 2011.
[Paper Link]

2010

#2010001
T. Yasufuku, T. Niiyama, Z. Piao, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, "Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits ," IEICE Transaction on Electronics, E93-C, No.3, pp.332-339, March 2010
[Paper Link]

#2010002
Yasufuku, K. Ishida, S. Miyamoto, H. Nakai, M. Takamiya, and T. Sakurai, "Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories ," IEICE Transaction on Electronics, E93-C, No.3, pp.317-323, March 2010

#2010003
K. Ishida, N. Masunaga, Z. Zhou, T. Yasufuku, T. Sekitani, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "Stretchable EMI Measurement Sheet With 8 X 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 um Silicon CMOS LSIs for Electric and Magnetic Field Detection," IEEE Journal of Solid-State Circuits, Vol. 45, No. 1, pp. 249-259, Jan. 2010
[Paper Link]

#2010004
M. Takamiya, K. Onizuka, K. Ishida, and T. Sakurai, "DC-DC Converter Technologies for On-Chip Distributed Power Supply Systems - 3D Stacking and Hybrid Operation," Springer, pp. 221-247, 2010

#2010005
Y. Kato, T. Sekitani, Y. Noguchi, T. Yokota, M. Takamiya, T. Sakurai and T, Someya, "Large-Area Flexible Ultrasonic Imaging System With an Organic Transistor Active Matrix," IEEE Transactions on Electron Devices, Vol. 57, No. 5, pp. 995 - 1002, 2010
[Paper Link]

#2010006
L. Liu, Z. Zhou, T. Sakurai, and M. Takamiya, "A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS," IEICE Transaction on Electronics, E93-C, No.6, pp. 796-802, 2010
[Paper Link]

#2010007
Î“cŒõˆęC‘‰i’žŽũC‚‹ī—šCŠÖ’J‹BCŽu–ėŽŽũCƒcƒB[ƒVƒƒƒ“ƒO@ƒEƒeCƒNƒ‰[ƒN@ƒn[ƒQƒ“C‚‹{^Cõ’J—ē•vCũˆä‹MN, "2V—L‹@CMOS‰ņ˜H‚ƃCƒ“ƒNƒWƒFƒbƒgˆóü”zü‚ð—p‚Ē‚―ƒ†[ƒU[EƒJƒXƒ^ƒ}ƒCƒUƒuƒ‹EƒƒWƒbƒNEƒy[ƒp[," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņ, ICD2010-35Cpp. 115-119, 2010

#2010008
”Ļ’†‹P‹`CÎ“cŒõˆęCˆĀ•ŸģC‹{–{WŽĶC’†ˆäOlC‚‹{^Cũˆä‹MNC’|“āŒ’, "NANDƒ`ƒƒƒlƒ‹”ŒŸo‰ņ˜HEƒCƒ“ƒeƒŠƒWƒFƒ“ƒg‘‚Ŧž‚Ý“dˆģ”­ķ‰ņ˜H‚ð”õ‚Ķ‚―A60%‚‘ŽE4.2GbpsE24ƒ`ƒƒƒlƒ‹A3ŽŸŒģƒ\ƒŠƒbƒhEƒXƒe[ƒgEƒhƒ‰ƒCƒuiSSDj," “dŽqî•ņ’ʐMŠw‰ï, MŠw‹Z•ņ, ICD2010-55Cpp. 89-94, 2010

#2010009
‚‹{^CŽÂŒīqŽjCũˆä‹MN, "‹É’á“dˆģ“Ūė‚É‚æ‚é’áƒGƒlƒ‹ƒM[LSI," “dŽqî•ņ’ʐMŠw‰ïŽ, 93ŠŠC11†, pp. 943-94, 2010

#2010010
L. Liu, T. Sakurai, and M. Takamiya, "A Charge-Domain Auto- and Cross-Correlation Based IR-UWB Receiver with Power- and Area-efficient PLL for 62.5ps Step Data Synchronization in 65nm CMOS," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņ, ICD2010-120, pp. 125-129, 2010

#2010011
Y. Pu, X. Zhang, J. Huang, A. Muramatsu, M. Nomura, K. Hirairi, H. Takata, T. Sakurabayashi, S. Miyano, M. Takamiya, and T. Sakurai, "Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņ, ICD2010-122, pp. 135-140, 2010

#2010012
X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P. Chen, K. Watanabe, T. Sakurai, and M. Takamiya, "A 1-V Input, 0.2-V to 0.47-V Output Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņ, ICD2010-127, pp. 163-167, 2010

#2010013
’”GCÎ“cŒõˆęC’ĢMC‘åŒFN‰îC—Ŧ—ĮŸC‚‹{^Cũˆä‹MN, "‹N“Ū‰ņ˜H‚ÉŒü‚Ŋ‚―Šî”‡ƒoƒCƒAƒXŒ^ 0.18-V “ü—̓`ƒƒ[ƒWƒ|ƒ“ƒv‰ņ˜H," “dŽqî•ņ’ʐMŠw‰ïCMŠw‹Z•ņ, ICD2010-128, pp. 169-173, 2010

#2010014
K. Ishida, N. Masunaga, R. Takahashi, T. Sekitani, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "User Customizable Logic Paper (UCLP) with Sea-of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects," IEEE Journal of Solid-State Circuits, Vol.46, No.1, pp. 285-292, 2011
[Paper Link]

#2010015
L. Liu, T. Sakurai, and M. Takamiya, "A Charge-Domain Auto- and Cross-Correlation Based IR-UWB Receiver with Power- and Area-efficient PLL for 62.5ps Step Data Synchronization in 65nm CMOS," IEEE Symposium on VLSI Circuits, Hawaii, pp. 27-28, 2010
[Paper Link]

#2010016
H. Ishizaki, T. Araki, S. Takahashi, J. Ryu, S. Uchida, N. Yoshida, M. Takamiya and M. Mizuno, "FDM-based Wireless Source Synchronous 15-Mbps TRx with PLL-less Receiver and 1-mm On-chip Integrated Antenna for 1.25-cm Touch-and-Proceed Communication," IEEE Symposium on VLSI Circuits, Hawaii, pp. 73-74, 2010

#2010017
T. Hatanaka, K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai and K. Takeuchi, "A 60% Higher Write Speed, 4.2Gbps, 24-Channel 3D-Solid State Drive (SSD) with NAND Flash Channel Number Detector and Intelligent Program-Voltage Booster," IEEE Symposium on VLSI Circuits, Hawaii, pp. 233-234, 2010

#2010018
P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "0.18-V Input Charge Pump with Forward Body Biasing in Startup Circuit using 65nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp. 239-242, 2010
[Paper Link]

#2010019
Y. Okuma, K. Ishida, Y. Ryu, P.-H. Chen, K. Watanabe, M. Takamiya, and T. Sakurai, "0.5-V Input Digital LDO with 98.7% Current Efficiency and 2.7-ƒĘA Quiescent Current in 65nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp. 323-326, 2010
[Paper Link]

#2010020
N. Masunaga, K. Ishida, M. Takamiya, and T. Sakurai, "EMI Camera LSI (EMcam) with 12 x 4 On-Chip Loop Antenna Matrix in 65-nm CMOS to Measure EMI Noise Distribution with 60-ƒĘm Spatial Precision," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp. 449-452, 2010
[Paper Link]

#2010021
T. Sekitani, K. Ishida, N. Masunaga, R. Takahashi, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Sakurai, and T. Someya, "Organic CMOS Logic Papers with In-Field User Customizability," 2010 International Conference on Solid State Devices and Materials (SSDM), 2010

#2010022
M. Takamiya, K. Ishida, T. Sekitani, T. Someya, and T. Sakurai, "Design of Large Area Electronics with Organic Transistors," IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 500-503, 2010
[Paper Link]

#2010023
Y. Pu, X. Zhang, J. Huang, A. Muramatsu, M. Nomura, K. Hirairi, H. Takata, T. Sakurabayashi, S. Miyano, M. Takamiya, and T. Sakurai, "Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems," IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 625-631, 2010
[Paper Link]

#2010024
X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P.-H. Chen, K. Watanabe, T. Sakurai, and M. Takamiya, "A 1-V Input, 0.2-V to 0.47-V Output Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction," IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, pp. 61-64, 2010
[Paper Link]

#2010025
L. Liu, T. Sakurai, and M. Takamiya, "0.6V Voltage Doubler and Clocked Comparator for Correlation-based Impulse Radio UWB Receiver in 65nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, pp. 301-304, 2010
[Paper Link]

#2010026
K. Ishida, K. Takemura, K. Baba, M. Takamiya, and T. Sakurai, "3D Stacked Buck Converter with 15um Thick Spiral Inductor on Silicon Interposer for Fine-Grain Power-Supply Voltage Control in SiPfs," IEEE International Conference on 3D System Integration (3D IC), Munich, Germany, 2010

#2010027
G.-S. Kim, K. Ikeuchi, M. Daito, M. Takamiya, and T. Sakurai, "A High-Speed, Low-Power Capacitive-Coupling Transceiver for Wireless Wafer-Level Testing Systems," IEEE International Conference on 3D System Integration (3D IC), Munich, Germany, 2010
#2010028
M. Takamiya, K. Ishida, T. Sekitani, U. Zschieschang, H. Klauk, T. Someya, and T. Sakurai, "Large Area Electronics with Organic Transistors and Novel Interconnects: EMI Measurement Sheet with Stretchable Interconnects and User Customizable Logic Paper (UCLP) with Ink-Jet Printed Interconnects," International Display Workshop (IDW), Fukuoka, Japan, pp. 1577-1580, 2010
[Paper Link]

#2010029
X. Zhang, K. Ishida, M. Takamiya, and T. Sakurai, "An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 109-110, 2010

#2010030
P. -H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 95mV-Startup Step-up Converter with VTH-Tuned Oscillator by Fixed-Charge Programming and Capacitor Pass-On Scheme," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 216-217, 2010

#2010031
K. Ishida, T. -C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda, M. Takamiya, T. Someya, and T. Sakurai, "100-V AC Power Meter System-on-a-Film (SoF) Integrating 20-V Organic CMOS Digital and Analog Circuits with Floating Gate for Process Variation Compensation and 100-V Organic PMOS Rectifier," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 218-219, 2010

#2010032
ũˆä‹MN, "’áÁ”ï“d—͏WÏ‰ņ˜H‹Zp‚Ė“W–]," ŽŸĒ‘ナƒ\ƒOƒ‰ƒtƒ[ƒNƒVƒ‡ƒbƒv—\eW, pp.3-4, 2010

#2010033
•―“c‹MŽmC“‡–{‹gCr–Ø‹MOCũˆä‹MNC‚‹{^, "ŽĨ‹C‹Ī–•ûŽŪ‚Ė–ģü“d—Í“`‘——pƒRƒCƒ‹‚ð–ģü’ʐM‚Ö‰ž—p‚ĩ‚―uŽĨ‹C‹Ī–’ʐMv‚Ė’ņˆÄ," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, B-1-1, 2010

#2010034
‚‹ī—šCX“c—TŽiC‚‹{^Cũˆä‹MN, "“dŒđƒmƒCƒY‚Æ”züŠÔƒNƒƒXƒg[ƒNƒmƒCƒY‚Ė“dŒđ“dˆģˆË‘ķŦ‚ÉŠÖ‚·‚éˆęlŽ@," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, C-12-18, 2010

#2010035
—Ņ睍ŠC“‡–{‹gCũˆä‹MNC‚‹{^, "ŽĨ‹C‹Ī–ÂŒ^–ģü“d—Í“`‘—‚É‚Ļ‚Ŋ‚éˆĘ’u‚ļ‚ę‚ɃƒoƒXƒg‚Č‘—MƒRƒCƒ‹ƒAƒŒ[‚ĖƒI[ƒvƒ“EƒVƒ‡[ƒg§Œä•ûŽŪ‚Ė’ņˆÄ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, B-1-6C“Œ‹ž, 2010

#2010036
–{“cŒ’‘ū˜YCÎ“cŒõˆęC‰Đûj–õCŠÖ’J‹BC‚‹{^Cõ’J—ē•vCũˆä‹MN, "20V—L‹@CMOSƒIƒyƒAƒ“ƒv‚É‚Ļ‚Ŋ‚éƒtƒ[ƒeƒBƒ“ƒOƒQ[ƒg‚ð—˜—p‚ĩ‚―ƒvƒƒZƒX‚΂į‚‚Ŧ•âģ‹Zp‚Ė’ņˆÄ‚ÆŽĀØ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, C-12-30, 2010

#2010037
ˆĀ•ŸģC’†‘šˆĀŒĐC–p“NC‚‹{^Cũˆä‹MN, "’á“dŒđ“dˆģ—Ėˆæ‚É‚Ļ‚Ŋ‚éƒ`ƒbƒv“ā’x‰„ŽžŠÔ‚΂į‚‚Ŧ‚Ė‘Š’č," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, C-12-31, 2011

#2010038
•Ð‰Š’ž”VCˆĀ•ŸģCX“c—TŽiC•―“üF“ņC‰Đûj–õC‘šž“āC–ė‘šđOC‚‹{^CŽÂŒīqŽjCũˆä‹MN, "Å’á‰Â“Ū“dˆģ(VDDmin)‚Ė’á‚ĒƒtƒŠƒbƒvƒtƒƒbƒv‰ņ˜Hƒgƒ|ƒƒW[‚Ė’Tõ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, C-12-33, 2011

#2010039
“A‰_”ōCÄ“ĄŧC“n•Ó˜a‹IC‚‹{^Cũˆä‹MN, "0.35V, 4.1uW, 39MHz, 40nm CMOS…ŧ”­U‰ņ˜H‚ĖŽĀØ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, C-12-50, 2011

#2010040
‚‹{^CˆĀ•ŸģCX“c—TŽiCÎ“cŒõˆęCũˆä‹MN, "‹É’á“dˆģ“Ūė‚É‚æ‚é’ī’á“d—͉ņ˜HÝŒv‹Zp," 2011”Nt‹G‘æ58‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, 25p-KC-5C_“ސė, 2011

#2010041
P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "0.18-V Input Charge Pump with Forward Body Biasing," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, C-12-58, 2011

2009

#2009001
L. Liu, T. Sakurai and M. Takamiya,"A 1.28mW 100Mb/s Impulse UWB Receiver with Charge-Domain Correlator and Embedded Sliding Scheme for Data Synchronization," Symp. on VLSI Circuits, Paper#14-3, June 2009
#2009002
K.Ishida, N.Masunaga, Z.Zhou, T.Yasufuku T.Sekitani, U.Zschieschang, H.Klauk, M.Takamiya, T.Someya, and T.Sakurai, "A Stretchable EMI Measurement Sheet with 8 x 8 Coil Array, 2V Organic CMOS Decoder and -70dBm EMI Detection Circuits in 0.18um CMOS," ISSCC 2009 digest of technical papers, paper#28.3, pp.472-473, Feb.2009
#2009003
T.Sakurai, "Wireless Power," ISSCC 2009 digest of technical papers, p.519, Feb.2009
#2009004
T.Sakurai, "Variability and Ultra-low Voltage Logic Design," ISSCC 2009 digest of technical papers, Forum 4 Ultra-Low-Voltage Circuit Design, p.507, Feb.2009
#2009005
K.Ishida, T.Yasufuku, S.Miyamoto, H.Nakai, M.Takamiya, T.Sakurai, K.Takeuchi, "A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD," ISSCC 2009 digest of thecnical papers, paper#13.2, pp.238-241, Feb.2009
#2009006
Y.Sugimori, Y.Kohama, M.Saito, Y.Yoshida, N.Miura, H.Ishikuro, T.Sakurai, T.Kuroda, "A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking," ISSCC 2009 digest of thecnical papers,paper#13.5, pp.244-245, Feb.2009
#2009007
T.Hatanaka, R.Yajima, S.Sakaki, M.Takahashi, Qiu-Hong Li, T.Horiuchi, S.Wang, Kwi-Young Yun, M.Takamiya, T.Sakurai, "Highly Scalable Fe(Ferroelectronics)-NAND Cell with MFIS (Metal-Ferroelectrric-Insulatore-Semiconductor) Structure for Sub-10 nm tera-Bit Capacity NAND Flash Memories," Proceedings of International Symposium on Secure-Life Electronics, pp.357-359, Jan.2009
#2009008
Y.Nakamura, D.Levacq, L.Xiao, T.Minakawa, T.Niiyama, M.Takamiya, T.Sakurai,"1/5 Power Reduction by Post-Fabrication Tuning with Fine-Grained Body Biasing," Proceedings of International Symposium on Secure-Life Electronics, pp.403-407, Jan.2009
#2009009
M.Takamiya, L.Liu, T.Sekitani, Y.Noguchi, S.Nakano, K.Zaitsu, T.Kuroda, T.Someya, T.Sakurai, "Ultra Low Power Inorgranic-Organic Hybrid Circuits and Digital-Analog Mixed Circuits for Secure Life," Proceedings of International Symposium on Secure-Life Electronics, pp.415-420, Jan.2009
#2009010
L.Liu, Y.Miyamoto, Z.Zhou, K.Sakaida, J.Ryu, K.Ishida, M.Takamiya, and T.Sakurai ,"A 100Mbps, 0.19mW Asynchronous Threshold Detector with DC Power-Free Pulse Discrimination for Impulse UWB Receiver," Asia-South Pacific Design Automation Conference (ASP-DAC) ,Jan.2009
#2009011
âˆä“ck•ã, ‚‹{@^, ũˆä‹MN ,"‹ĪUƒNƒƒbƒN‚É‚Ļ‚Ŋ‚é’á‘ŽƒeƒXƒg‚Æ’á“d—͉ŧ‚ð—ž—§‚ģ‚đ‚éƒNƒƒbƒN•Š”z‰ņ˜H‚Ė’ņˆÄ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï ,ˆĪ•QŒ§žŽRŽs,2009”N3ŒŽ18“ú
#2009012
Î“cŒõˆę, ˆĀ•Ÿ@ģ, ‚‹{@^, ’|“ā@Œ’, ũˆä‹MN,"NANDŒ^ƒtƒ‰ƒbƒVƒ…SSDŒü‚Ŋ20Vƒu[ƒXƒgƒRƒ“ƒo[ƒ^‚Ė§Œä•ûŽŪ(‚ŧ‚Ė1)," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, ˆę”ʍu‰‰,2009”N3ŒŽ
#2009013
ˆĀ•Ÿ@ģ, Î“cŒõˆę, ‚‹{@^, ’|“ā@Œ’, ũˆä‹MN ,"NANDŒ^ƒtƒ‰ƒbƒVƒ…SSDŒü‚Ŋ20Vƒu[ƒXƒgƒRƒ“ƒo[ƒ^‚Ė§Œä•ûŽŪ(‚ŧ‚Ė2)," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï ,ˆĪ•QŒ§žŽRŽs, 2009”N3ŒŽ18“ú
#2009014
’r“āŽ”V, ˆîŠ_ŒŦˆę, ‘ŒõGŽũ, ˆÉ“Œ—˜ˆį, ‚‹{@^, ũˆä‹MN ,"”ņÚGƒRƒlƒNƒ^Œü‚Ŋ500Mbps—e—ĘŒ‹‡’ʐM—pŽóM‰ņ˜H‚ĖŒŸ“Ē," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï ,ˆĪ•QŒ§žŽRŽs, 2009”N3ŒŽ18“ú
#2009015
‘‰i’žŽũ, Î“cŒõˆę, Žü@ŽuˆĖ, ˆĀ•Ÿ@ģ, ŠÖ’J@‹B, ‚‹{@^, õ’J—ē•v, ũˆä‹MN ,"Lk‰Â”\‚ČEMI‘Š’čƒV[ƒg‚É‚Ļ‚Ŋ‚éEMI‘Š’č—pLSI‚ĖÝŒv‚Æ•]‰ŋ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï ,ˆĪ•QŒ§žŽRŽs,2009”N3ŒŽ
#2009016
ũˆä‹MN, "VLSIÝŒvŒĪ‹†‚Å‚Ė‘ÛŽYŠw˜AŒg,CCR12”N‚Ė‹OÕ," Mar-08.2009
#2009017
ũˆä‹MN, "Åæ’[‹Zp‚É‚Ļ‚Ŋ‚éƒfƒoƒCƒX‚΂į‚‚Ŧ‚Æ“Œv“I‰ņ˜H“ÁŦ," ƒVƒXƒeƒ€ƒfƒUƒCƒ“ƒtƒH[ƒ‰ƒ€2009,ƒpƒVƒtƒBƒR‰Ą•lƒAƒlƒbƒNƒXƒz[ƒ‹ ,Jan-09, 2009
#2009018
ũˆä‹MN, "ŠŠ“Š‘Î’k@”ž“ą‘Ė‚ĖŦ—ˆ‚Æ’áÁ”ï“d—͉ŧ‚Ė•K—vŦ," Vol.23,,Feb-09, 2009
#2009019
Y.Sugimori, Y.Kohama, M.Saito, Y.Yoshida, N.Miura, H.Ishikuro, T.Sakurai, T.Kuroda, "A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking," ISSCC'09, paper#13.5, pp.244-245, Feb.2009
#2009020
K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T.Sakurai, K. Takeuchi, "A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD," ISSCC'09, paper#13.2, pp.238-241, Feb.2009
#2009021
K. Ishida, N. Masunaga, Z. Zhou, T. Yasufuku, T. Sekitani, U.Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "A Stretchable EMI Measurement Sheet with 8 x 8 Coil Array, 2V Organic CMOS Decoder, and -70dBm EMI Detection Circuits in 0.18um CMOS," ISSCC'09, paper#28.3, pp.472-473, Feb.2009
#2009022
T. Sakurai, "Variability and Ultra-low Voltage Logic Design," ISSCC'09, Forum 4: Ultra-Low-Voltage Circuit Design, p.507, Feb. 2009
#2009023
T.Sakurai, "Wireless Power," ISSCC'09, Special Evening session 7: Next Generation Energy Scavenging Systems, p.519, Feb. 2009
#2009024
N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, and T. Kuroda, "A High-Speed Inductive-Coupling Link with Burst Transmission," IEEE Journal of Solid-State Circuits (JSSC), vol.44, no.3, pp.947-955, Mar. 2009
#2009025
G.-S. Kim, M. Takamiya, and T. Sakurai, "A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems," IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 56, No. 9, pp. 709 - 713, Sep. 2009
#2009026
Takao Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takayasu Sakurai, Ute Zschieschang and Hagen Klauk, "Printed organic transistors: Toward ambient electronics," Plenary talk, IEDM, Dec. 2009
#2009027
ũˆä‹MN, b”ãNŽi, “Ą“‡ŽĀ, "2020”N‚ĖŦ—ˆ‘œ 2020”N‚Ė”ž“ą‘Ė-ƒAƒvƒŠƒP[ƒVƒ‡ƒ“‘―—l‰ŧ‚Ö‚Ė’§í," ”ž“ą‘Ė‹Zp”NŠÔ2010 ƒfƒoƒCƒX/ƒvƒƒZƒX•Ō, pp.11-20, “úŒoBPŽÐ, Nov. 2009
#2009028
ũˆä‹MN, "ƒƒWƒbƒN‰ņ˜H ÝŒv‚Đ‚įŒĐ‚―ƒgƒ‰ƒ“ƒWƒXƒ^‚Ėƒoƒ‰‚‚Ŧ‚Æ‹É’á“dˆģƒƒWƒbƒN," ”ž“ą‘Ė‹Zp”NŠÔ2010 ƒfƒoƒCƒX/ƒvƒƒZƒX•Ō, pp.87-94, “úŒoBPŽÐ, Nov. 2009
#2009029
L. Liu, M. Takamiya, T. Sekitani, Y. Noguchi, S. Nakano, K. Zaitsu, T. Kuroda, T. Someya, and T. Sakurai, "A 107-pJ/bit 100-kb/s 0.18-um Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet," IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 56, No. 11, pp. 2511 - 2518, Nov. 2009
#2009030
‚‹{@^, ŠÖ’J@‹B, õ’J—ē•v, ũˆä‹MN, "ƒƒCƒ„ƒŒƒX“d—Í“`‘—E’ʐMƒV[ƒg," “ú–{ŽĨ‹CŠw‰ï‰ï•ņu‚Ü‚Ū‚ˁv, Vol. 4, No. 9, pp.435-440, Sep. 2009
#2009031
Sanghoon Hwang, Hyunsik Im, Minkyu Song, Koichi Ishida, Toshiro Hiramoto, and Takayasu Sakurai, "Velocity Saturation Effects in a Short Channel Si- MOSFET and its Small Signal Characteristics," Journal of the Korean Physical Society, Vol.55, No.2, pp.581-584, Aug. 2009
#2009032
Y. Nakamura, M. Takamiya, and T. Sakurai, "An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise," IEICE Transaction on Electronics, E92-C, No.4, pp.468-472, Apr. 2009
#2009033
L. Liu, Y. Miyamoto, Z. Zhou, K. Sakaida, J. Ryu, K. Ishida, M. Takamiya, and T. Sakurai, "100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS," IEICE Transaction on Electronics, E92-C, No.6, pp.769-776, Jun. 2009
#2009034
T. Sekitani, K. Zaitsu, Y. Noguchi, K. Ishibe, M. Takamiya, T. Sakurai, and T. Someya, "Printed Nonvolatile Memory for a Sheet-Type Communication System," IEEE Transactions on Electron Devices, Vol. 56, No. 5, pp. 1027 - 1035, May 2009
#2009035
ũˆä‹MN, •“c’‰L, “đŠÖ—ē‘, "CMOS LSI’á“d—͉ņ˜H‹Zp‚Ėæ‹ė“IŠJ”­‚ÆŽĀ—p‰ŧ," “dŽqî•ņ’ʐMŠw‰ïŽ, Vol.92, N0.7, pp.506-507, Jul. 2009
#2009036
M. Daito, Y. Nakata, S. Sasaki, H. Gomyo, H. Kusamitsu, Y. Komoto, K. Iizuka, K. Ikeuchi, G. Kim, M. Takamiya, and T. Sakurai, "Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing," IEEE International Solid-State Circuits Conference (ISSCC), pp. 144-145, 2009
#2009037
T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K. Takeuchi, M. Takamiya, T. Sakurai, and T. Someya, "Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays," Science, Vol. 326, pp.1516-1519, 2009
#2009038
T. Someya, T. Sekitani, M. Takamiya, T. Sakurai, U. Zschieschang, and H. Klauk, "Printed Organic Transistors: Toward Ambient Electronics," IEEE International Electron Devices Meeting (IEDM), pp. 9-14, 2009
#2009039
Makoto Suzuki, Takuya Saraya, Ken Shimizu, Takayasu Sakurai, and Toshiro Hiramoto, "Improvement of Static Noise Margin in SRAM by Post-Fabrication Self-Convergence Technique," International Semiconductor Device Research Symposium (ISDRS), TP7-03, 2009
#2009040
G.-S. Kim, M. Takamiya, and T. Sakurai, "A Capacitive Coupling Interface with High Sensitivity for Wireless Wafer Testing," IEEE International Conference on 3D System Integration (3D IC), 2009
#2009041
T. Yasufuku, K. Ishida, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "Effect of Resistance of TSVfs on Performance of Boost Converter for Low Power 3D SSD with NAND Flash Memories," IEEE International Conference on 3D System Integration (3D IC) , 2009
#2009042
K. Ikeuchi, K. Sakaida, K. Ishida, T. Sakurai, and M. Takamiya, "Switched Resonant Clocking (SRC) Scheme Enabling Dynamic Frequency Scaling and Low-Speed Test," IEEE Custom Integrated Circuits Conference (CICC), pp. 33-36, 2009
#2009043
T. Yasufuku, K. Ishida, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "Inductor Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories," International Symposium on Low Power Electronics and Design (ISLPED), pp. 87-91, 2009
#2009044
N. Masunaga, K. Ishida, Z. Zhou, T. Yasufuku, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "A Flexible EMI Measurement Sheet to Measure Electric and Magnetic Fields Separately with Distributed Antennas and LSIfs," IEEE International Symposium on Electromagnetic Compatibility, pp. 156-160, 2009
#2009045
L. Liu, T. Sakurai, and M. Takamiya, "A 1.28mW 100Mb/s Impulse UWB Receiver with Charge-Domain Correlator and Embedded Sliding Scheme for Data Synchronization," IEEE Symposium on VLSI Circuits, pp. 146-147, 2009
#2009046
Makoto Suzuki, Takuya Saraya, Ken Shimizu, Takayasu Sakurai, and Toshiro Hiramoto, "Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors," Symposium on VLSI Technology, pp.148-149, 2009
#2009047
T. Sakurai, "Next-Generation Power-Aware Integrated Circuit Design," International Meeting for Future of Electron Devices Kansai (IMFEDK), K-3, pp.18-21, 2009
#2009048
ˆĀ•Ÿ ģ, Î“cŒõˆę, ‹{–{WŽĶ, ’†ˆäOl, ‚‹{ ^, ũˆä‹MN, ’|“ā Œ’, "ŽOŽŸŒģSSD—p20Vƒu[ƒXƒgƒRƒ“ƒo[ƒ^Œü‚Ŋ‚ĖƒCƒ“ƒ_ƒNƒ^ÝŒv," “dŽqî•ņ’ʐMŠw‰ï, MŠw‹Z•ņ, ICD2009-103, pp. 151-156, Nov. 2009
#2009049
Î“cŒõˆę, ‘‰i’žŽũ, Žü@ŽuˆĖ, ˆĀ•Ÿ@ģ, ŠÖ’J@‹B, ƒcƒB[ƒVƒƒƒ“ƒO ƒEƒe, ƒNƒ‰[ƒN ƒn[ƒQƒ“, ‚‹{@^,õ’J—ē•v, ũˆä‹MN, "2V—L‹@CMOS‚ƃVƒŠƒRƒ“CMOS‚ð—p‚Ē‚―EMI‘Š’č—p•—˜C•~‚ĖŒī—ŒŸØ," “dŽqî•ņ’ʐMŠw‰ï, MŠw‹Z•ņ, ICD2009-33, pp. 1-6, Oct. 2009
#2009050
L. Liu, T. Sakurai, and M. Takamiya, "A 100Mbps, 1.28mW Impulse Radio UWB Receiver with Charge-Domain Sampling Correlator in 0.18um CMOS," “dŽqî•ņ’ʐMŠw‰ï, MŠw‹Z•ņ, ICD2009-14, pp.7-11, Jul. 2009
#2009051
—é–ؐ―, X‰Ū‘ņÆ, ī…Œ’, ũˆä‹MN, •―–{r˜Y, "SRAM‚Ļ‚æ‚ŅƒƒWƒbƒNƒgƒ‰ƒ“ƒWƒXƒ^‚É‚Ļ‚Ŋ‚é“ÁŦ‚΂į‚‚ŦˆęŠ‡ŽĐŒČC•œŽč–@," ‰ž—p•Ļ—Šw‰ïƒVƒŠƒRƒ“ƒeƒNƒmƒƒW[•Š‰Č‰ïŒĪ‹†W‰ï, pp.32-35, Jul. 2009
#2009052
‘‰i’žŽũCÎ“cŒõˆęCŽü ŽuˆĖCˆĀ•Ÿ ģCŠÖ’J ‹BCZschieschang UteCKlauk HagenC‚‹{ ^Cõ’J—ē•vCũˆä‹MN, "8~8‚ĖƒRƒCƒ‹ƒAƒŒ[‚Æ2V—L‹@CMOSƒfƒR[ƒ_‚ÆEMIŒŸo—pLSI‚ō\Ž‚ģ‚ę‚―Lk‰Â”\‚ČEMI‘Š’čƒV[ƒg‚Ė’ņˆÄ‚Æ“ŪėŽĀØ," “dŽqî•ņ’ʐMŠw‰ïALSI‚ƃVƒXƒeƒ€‚Ėƒ[ƒNƒVƒ‡ƒbƒv-267iIEEE SSCS Kansai Chapter Award ŽóÜj, ƒ|ƒXƒ^[ƒZƒbƒVƒ‡ƒ“ Šwķ•”–å28, pp. 265-267, May 2009
#2009053
ˆĀ•Ÿ ģ,Î“cŒõˆę,‹{–{WŽĶ,’†ˆäOl,‚‹{ ^,ũˆä‹MN,’|“ā Œ’, "ŽOŽŸŒģÏ‘wNANDŒ^ƒtƒ‰ƒbƒVƒ…SSDŒü‚ŊƒvƒƒOƒ‰ƒ€“dˆģ(20V)ķŽ‰ņ˜H," “dŽqî•ņ’ʐMŠw‰ïALSI‚ƃVƒX ƒeƒ€‚Ėƒ[ƒNƒVƒ‡ƒbƒv, ƒ|ƒXƒ^[ƒZƒbƒVƒ‡ƒ“ Šwķ•”–å27iICD—DG”­•\Ü ŽóÜj, pp. 262-264, May 2009
#2009054
ˆĀ•Ÿ ģ,Î“cŒõˆę,‹{–{WŽĶ,’†ˆäOl,‚‹{ ^,ũˆä‹MN,’|“ā Œ’, "ŽOŽŸŒģSSD‚Ė’á “d—͉ŧ‹Zp‚ÆSSD Œü‚ŊƒvƒƒOƒ‰ƒ€“dˆģ(20V)ķŽ‰ņ˜H," “dŽqî•ņ’ʐMŠw‰ïAMŠw‹Z•ņ, ICD2009-10, pp. 47-52, Apr. 2009
#2009055
ũˆä‹MN, "ÝŒv‚Đ‚įŒĐ‚―ƒgƒ‰ƒ“ƒWƒXƒ^‚Ė‚΂į‚‚Ŧ‚Æ‹É’á“dˆģƒƒWƒbƒN," “úŒoƒZƒ~ƒi[, pp.67-87, Jul. 2009
#2009056
ũˆä‹MN, "ƒOƒŠ[ƒ“‰ŧ‚ĖØ‚čŽDF‹É’á“d—͉ņ˜HEƒVƒXƒeƒ€‹Zp," STARC ƒtƒH[ƒ‰ƒ€ƒVƒ“ƒ|ƒWƒEƒ€ 2009, pp.59-73, Aug. 2009
#2009057
ũˆä‹MN, "‘gž‚݃n[ƒhƒEƒFƒA‚ĖĄŒã‚ÆŒĪ‹†ƒrƒWƒ‡ƒ“," î•ņˆ—Šw‰ïƒZƒ~ƒi[ 2009, No.5, pp.171-20, Sep. 2009
#2009058
’r“āŽ”VCˆîŠ_ŒŦˆęC‘ŒõGŽũCˆÉ“Œ—˜ˆįC‚‹{@^Cũˆä‹MN, "”ņÚGƒRƒlƒNƒ^Œü‚Ŋ500Mbps—e—ĘŒ‹‡’ʐM—pŽóM‰ņ˜H‚ĖŒŸ“Ē," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, Mar. 2009
#2009059
Î“c ŒõˆęCˆĀ•Ÿ@ģC‚‹{@^C’|“ā@Œ’Cũˆä‹MN, "NANDŒ^ƒtƒ‰ƒbƒVƒ…SSDŒü‚Ŋ20Vƒu[ƒXƒgƒRƒ“ƒo[ƒ^‚Ė§Œä•ûŽŪi‚ŧ‚Ė‚Pj," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, Mar. 2009
#2009060
ˆĀ•Ÿ@ģCÎ“cŒõˆęC‚‹{@^C’|“ā@Œ’Cũˆä‹MN, "NANDŒ^ƒtƒ‰ƒbƒVƒ…SSDŒü‚Ŋ20Vƒu[ƒXƒgƒRƒ“ƒo[ƒ^‚Ė§Œä•ûŽŪi‚ŧ‚Ė‚Qj," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, Mar. 2009
#2009061
âˆä“c k•ãC‚‹{@^Cũˆä ‹MN, "‹ĪUƒNƒƒbƒN‚É‚Ļ‚Ŋ‚é’á‘ŽƒeƒXƒg‚Æ’á“d—͉ŧ‚ð—ž—§‚ģ‚đ‚éƒNƒƒbƒN•Š”z‰ņ˜H‚Ė’ņˆÄ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, Mar. 2009
#2009062
ũˆä‹MN,"”ž“ą‘Ė‚ĖV‹Zp‚Æ–Ē—ˆ," ”ž“ą‘Ė/”ũŨ‰ÁH•Š–ėu‰‰‰ï, Mar.5, 2009

2008

#2008001
S.D.Choi, K. Ikeuchi, H.K.Kim, K.Inagaki, M. Takamiya, T.Sakurai,gExperimental Assessment of Logic Circuit Performance Variability with Regular Fabrics at 90nm Technology Node,hESSCIRC, A2L-A1, Sept. 2008
#2008002
Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, and Takayasu Sakurai, "Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and Its Implications in Low Power DFM," Proc. 9th International Symposium on Quality Electronic Design, March, 2008
#2008003
L.Liu, M.Takamiya, T.Sekitani, Y.Noguchi, S.Nakano, K.Zaitsu, T.Kuroda, T.Someya, and T.Sakurai, "A 107pJ/bit 100kbps 0.18um Capacitive Coupling Transceiver with Asynchronous Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet," ISSCC'08, pp.292-293, Feb.2008
#2008004
N.Miura, Y.Kohama, Y.Sugimori, H.Ishikuro, T.Sakurai, and T.Kuroda, "An 11Gb/s Inductive-Coupling Link with Burst Transmission," ISSCC'08, pp.298-299, Feb.2008
#2008005
T. Niiyama, P. Zhe, K.Ishida, M. Murakata, M. Takamiya, and T. Sakurai, "Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and Its Implications in Low Power DFM," Proc. 9th International Symposium on Quality Electronic Design (ISQED), pp. 136-136, March, 2008
#2008006
T. Niiyama, P. Zhe, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, gIncreasing Minimum Operating Voltage (VDDmin) with Number of CMOS Logic Gates and Experimental Verification with up to 1Mega-Stage Ring Oscillators," ISLPED'08, pp.117-122, Aug. 2008
#2008007
L.Liu, Y.Miyamoto, Z.Zhou, K.Sakaida, R.Jisun, K.Ishida, M.Takamiya and T.Sakurai, "A 100Mbps, 0.41mW, DC-960MHz Band Impulse UWB Transceiver in 90nm CMOS," Symp. on VLSI Circuits, June 2008
#2008008
Y.Nakamura, D.Levacq, L.Xiao, T.Minakawa, T.Niiyama, M.Takamiya, and T.Sakurai, "1/5 Power Reduction by Global Optimization based on Fine-Grained Body Biasing," CICC'08, pp. 547-550, Sept. 2008
#2008009
K.Ikeuchi, K.Inagaki, H.Kusamitsu, T.Ito, M.Takamiya, and T.Sakurai, "500Mbps, 670uW/pin Capacitively Coupled Receiver with Self Reset Scheme for Wireless Connectors," A-SSCC'08, pp.93-96, Nov. 2008
#2008010
T.Sakurai, "Next-Generation Power-Aware Design (Plenary Talk)", ISLPED08, Aug. 13, Bangalore, India.
#2008011
T.Sakurai, "Solving Issues of Integrated Circuits by 3D-Stacking Meeting with the Era of Power, Integrity Attackers and NRE Explosion and a Bit of Future (Pleanary Talk)," ESSCIRC, B4L-A1, Sept. 2008
#2008012
M.Takamiya, T.Sekitani, Y.Miyamoto, Y.Noguchi, H.Kawaguchi, T.Someya, T.Sakurai, "Design of Wireless Power Transmission Sheet with Organic FETs and Plastic MEMS Switches," Proceedings of International Symposium on Secure-Life Electronics, pp.557-561, Mar.2008
#2008013
K.Onizuka, M.Takamiya, T.Sakurai,"Recent Progress in On-Chip Power Supply Circuits," Proceedings of International Symposium on Secure-Life Electronics, pp.563-569, Mar.2008
#2008014
T.Niiyama, K.Ishida, M.Takamiya, T.Sakurai,"Expected Vectorless Teacher-Student Swap(TSS) Test method with Dual Power Supply Voltages for 0.3V Homogeneous Multi-core LSI's," IEEE 2008 Custom Inegrated Circuits Conference, Paper#8.5, pp.137-140, Sept.2008
#2008015
T.Sakurai, "Solving Issues of LSI by 3-Dimensional System-in-Package (Plenary talk)," International Conference on Electronics Packaging, Jan.2008
#2008016
T.Someya, T.Sekitani, M.Takamiya, T.Sakurai ,"Recent Progress of Wireless Transmission Systems Using Printed Plastic MEMS Switches and Organic Transistors," Eighth International Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS + microEMS 2008), Nov.2008
#2008017
Y.Kato, T.Sekitani, Y.Noguchi, M.Takamiya, T.Sakurai, T. Someya ,"A large-area, flexible, ultrasonic imaging system with a printed organic transistor active matrix," IEEE International Electron Devices Meeting (IEDM) ,Paper#4.7, Dec.2008
#2008018
N.Miura, Y.Kohama, Y.Sugimori, H.Ishikuro, T.Sakurai, and T.Kuroda, "An 11Gb/s Inductive-Coupling Link with Burst Transmission," ISSCC'08 digest of technical papers, pp.298-299, Feb.2008
#2008019
N.Miura, H.Ishikuro, K.Niitsu, T.Sakurai, and T.Kuroda, "A 0.14pJ/b Inductive-Coupling Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE Journal of Solid-State Circuits (JSSC), vol.43, no.1, pp.285-291, Jan. 2008
#2008020
T.Sakurai, "Next-Generation Power-Aware Design (Plenary Talk)," ISLPED'08, Bangalore, India, Aug.2008
#2008021
T.Sakurai, "Variability and Ultra-low Voltage Logic Design," ISSCC 2009 digest of technical papers, Forum 4 Ultra-Low-Voltage Circuit Design, p.507, Feb.2008
#2008022
ŠÖ’J‹BAUte Zschieschang, Hagen Klauk, ‚‹{^Aũˆä‹MNAõ’J—ē•v ,"—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ėˆóüŧ‘ĒEM—ŠŦ‚ƃtƒŒƒLƒVƒuƒ‹ƒfƒoƒCƒX‚Ö‚Ė‰ž—p," ƒ|ƒŠƒ}[ƒtƒƒ“ƒeƒBƒA21 ƒvƒ‰ƒXƒ`ƒbƒNƒGƒŒƒNƒgƒƒjƒNƒXÅ‘Oü@`ƒtƒŒƒLƒVƒuƒ‹ƒfƒoƒCƒX‚Ö‚Ė“W–] ,‚•ŠŽqŠw‰ï,2008
#2008023
b”ãNŽiA“Ą“‡ŽĀAũˆä‹MN, "2025”N‚Ė”ž“ą‘Ė‹Zp ’N‚Š‰―‚ðė‚é‚Ė‚Đ uƒ}ƒCƒNƒƒLƒ…[ƒuEƒ`ƒbƒvv uƒCƒ“ƒ`Eƒtƒ@ƒuv," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX“Á•Ę•ŌW”Å, Aug.2008
#2008024
"WÏ‰ņ˜H‚Ė‹ß–Ē—ˆ," “úŒoŽY‹ÆV•·, 2008”N8ŒŽ21“ú
#2008025
ũˆä‹MN, "WÏ‰ņ˜H‚ĖŦ—ˆ‚Ɖۑč," JissoƒtƒH[ƒ‰ƒ€2008,ƒAƒpƒzƒeƒ‹•ƒŠƒ][ƒg “Œ‹žƒxƒC–‹’Ģƒz[ƒ‹ ,2008
#2008026
ũˆä‹MN, "Si-LSI‚ĖŦ—ˆ‹Zp“ŪŒü ,‚RŽŸŒģÏ‘w‚É‚æ‚éWÏ‰ņ˜H‚Ė‰Û‘č‰ðŒˆ," “ú—§ŧėŠ‘‡‹ģˆįƒZƒ“ƒ^[ ,2008
#2008027
ũˆä‹MN, "‚RŽŸŒģSiP‚ĖŠJ”­“ŪŒü‚ƏŦ—ˆ“W–]," ‚RŽŸŒģLSI/SiP/PoPu‰‰,‘•]‰ïŠŲ ,Apr-08.2008
#2008028
ũˆä‹MN, "’á“d—͏WÏ‰ņ˜H‚ĖÅ‹ß‚Ė˜b‘č," ”ž“ą‘ĖƒVƒjƒA‹Ķ‰ï“Á•Ęu‰‰‰ï,Sep-08. 2008
#2008029
ũˆä‹MN, "V‚―‚Č“WŠJ‚ðŒĐ‚đ‚éŽOŽŸŒģWÏ‰ŧ‹Zp,"TEL Advanced Technology Forum 2008,“Œ‹žƒGƒŒƒNƒgƒƒ“ŽR—œŽ–‹ÆŠ ,Sep-08, 2008
#2008030
ũˆä‹MN, "’á“d—͏WÏ‰ņ˜H‚ĖÅ‹ß‚Ė˜b‘č," SSIS2008”N“xŽ^•‰ïˆõ˜A—‰ï“Á•Ęu‰‰‰ï, Oct-08, 2008
#2008031
b”㠍NŽiA“Ą“‡ ŽĀAũˆä ‹MN, "2025”N‚Ė”ž“ą‘Ė‹Zp’N‚Š‰―‚ðė‚é‚Ė‚Ёuƒ}ƒCƒNƒƒLƒ…[ƒuEƒ`ƒbƒvvuƒCƒ“ƒ`Eƒtƒ@ƒuv," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX“Á•Ę•ŌW”Å, Aug. 2008
#2008032
Y.Kato, T.Sekitani, Y.Noguchi, M.Takamiya, T.Sakurai, T. Someya, "A large-area, flexible, ultrasonic imaging system with a printed organic transistor active matrix," IEEE International Electron Devices Meeting (IEDM), #4.7, Dec. 2008
#2008033
N. Miura, H. Ishikuro, K. Niitsu, T. Sakurai, and T. Kuroda, "A 0.14pJ/b Inductive-Coupling Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE Journal of Solid-State Circuits (JSSC), vol.43, no.1, pp.285-291, Jan. 2008
#2008034
‘‰i’žŽũCÎ“cŒõˆęCŽü@ŽuˆĖCˆĀ•Ÿ@ģCŠÖ’J@‹BC‚‹{@^Cõ’J—ē•vCũˆä‹MN, "Lk‰Â”\‚ČEMI‘Š’čƒV[ƒg‚É‚Ļ‚Ŋ‚éEMI‘Š’č—pLSI‚ĖÝŒv‚Æ•]‰ŋ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, Mar. 2008
#2008035
ŠÖ’J‹BAUte Zschieschang, Hagen Klauk, ‚‹{^Aũˆä‹MNAõ’J—ē•v, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ėˆóüŧ‘ĒEM—ŠŦ‚ƃtƒŒƒLƒVƒuƒ‹ƒfƒoƒCƒX‚Ö‚Ė‰ž—p," ƒ|ƒŠƒ}[ƒtƒƒ“ƒeƒBƒA21 ƒvƒ‰ƒXƒ`ƒbƒNƒGƒŒƒNƒgƒƒjƒNƒXÅ‘Oü@`ƒtƒŒƒLƒVƒuƒ‹ƒfƒoƒCƒX‚Ö‚Ė“W–], ‚•ŠŽqŠw‰ï, Sep. 2008
#2008036
ũˆä‹MN,"“Œ‘å‚ŠƒV[ƒgó‚Ė’ʐM”}‘Ė‚ðŠJ”­@—Lü‚Æ–ģü‚Ė‘g‚ݍ‡‚í‚đ‚ŏÁ”ï“d—͍íŒļ," EETIMES Japan,no.32, p.20, 2008
#2008037
ũˆä‹MN,"i“Á•Ęƒƒ“ƒOƒCƒ“ƒ^ƒrƒ…[)‰æŠú“Iƒ[ƒpƒ[A‘å–ĘÏƒGƒŒƒNƒgƒƒjƒNƒX‚ð’Į‹," ”ž“ą‘ĖŽY‹ÆV•·, Feb.6, 2008
#2008038
ũˆä‹MN,"i“Á•Ęƒƒ“ƒOƒCƒ“ƒ^ƒrƒ…[)ƒ[ƒpƒ[‚ĖŒˆ‚ߎč‚́u“dŒđv‚Ė“dˆģƒRƒ“ƒgƒ[ƒ‹," ”ž“ą‘ĖŽY‹ÆV•·, Feb.13, 2008

2007

#2007001
Takayasu Sakurai, "Meeting with the Forthcoming IC Design - The Era of Power, Variability and NRE Explosion and a Bit of the Future," Asia and South Pacific Design Automation Conference, pp.viii, Jan. 2007
#2007002
Takayasu Sakurai, "Advances in Low-Power Integrated Circuits and Large-Area Electronics for Ubiquitous Electrinics-Solving Issues with 3D-Stacking-," Proceedings of COE Sympoium on Advanced Electtrinics for Future Generations, 1, pp.89-94, Jan. 2007
#2007003
M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display," IEEE Journal of Solid-State Circuits, Vol.42, No.1, pp.93-100, Jan. 2007
#2007004
N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "A 1 Tb/s 3W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link," IEEE Journal of Solid-State Circuits, Vol.42, No.1, pp.111-122, Jan. 2007
#2007005
Takayasu Sakurai, "Organic-Transistor Circuit Design," IEEE International Solid-State Circuits Conference , U.S.A., T8, Feb. 11, 2007
#2007006
M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, and T. Sakurai, "Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches," IEEE International Solid-State Circuits Conference, pp.362-609, Feb. 2007
#2007007
N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE International Solid-State Circuits Conference, pp.358-608, Feb. 2007
#2007008
Y. Kato, T. Sekitani, M. Takamiya, M. Doi, K. Asaka, T. Sakurai, and T. Someya, "Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators," IEEE Transactions on Electron Devices, Vol.54, No.2, pp.202-209, Feb. 2007
#2007009
N. Miura, T. Sakurai, and T. Kuroda, "Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array," IEEE Journal of Solid-State Circuits, Vol.42, No.2, pp.410-421, Feb. 2007
#2007010
ũˆä‹MN, "“dŒđƒP[ƒuƒ‹‚ðŽg‚í‚ļ‚É“d—Í‹Ÿ‹‹@“Œ‘å‚Š“d—Í“`‘——pƒV[ƒg‚ðŠJ”­," EETIMES Japan, 20, pp.16, Feb. 2007
#2007011
ũˆä‹MN, "i“Á•Ęu‰‰jÝŒv‚Đ‚įŒĐ‚―3ŽŸŒģSiPƒ\ƒŠƒ…[ƒVƒ‡ƒ“," ”ž“ą‘Ėƒ[ƒhƒ}ƒbƒvę–åˆÏˆõ‰ï@‘æˆę•”@ITRS2006@Update‚ÉŒĐ‚éĄŒã‚ĖLSI‹Zp‚Ė•ûŒüŦ, ƒRƒNƒˆƒz[ƒ‹, 8F, Mar. 8, 2007
#2007012
ũˆä‹MN, "”ž“ą‘Ėƒxƒ“ƒ`ƒƒ[—ņ“`," “Œ—mŒoÏ, pp.277, Mar. 8, 2007
#2007013
VŽR‘ū˜Y, ‚‹{^, ũˆä‹MN, "’ī’á“dˆģ—Ėˆæ‚É‚Ļ‚Ŋ‚郊ƒ“ƒOƒIƒVƒŒ[ƒ^‚Ė”­UŽü”g”‚΂į‚‚Ŧ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, –žé‘åŠw, C-12-14, pp.93, Mar. 21, 2007
#2007014
Takayasu Sakurai, "Sloving issues of VLSI by 3D-SiP-From design perspective," Technical Digest of the International 3D System Integration Conference, Tokyo, 14, Mar. 27, 2007
#2007015
Kazuki Hizu, Tsuyoshi Sekitani, Joe Otsuki, Makoto Takamiya, Takayasu Sakurai, and Takao Someya, "Air-stable operation of organic complementary circuits on a polyimide film," The Fourth International Conference on Molecular Electronics and Bioelectronics (M&BE4), Mar. 2007
#2007016
Y. Kato, T. Sekitani, M. Takamiya, M. Doi, K. Asaka, T. Sakurai, and T. Someya, "Integration of organic semiconducting nano-materials and polymer actuators and their application," 2007 Frontiers in Nanoscale Science and Technology, Tokyo, A15, Mar. 2007
#2007017
‹S’ˍ_•―, ũˆä‹MN, "’á“d—́E’áƒRƒXƒg‚ČŽOŽŸŒģÏ‘wLSI‚Ė‚―‚ß‚ĖƒIƒ“ƒ`ƒbƒv“dŒđ‰ņ˜H‹Zp," “Œ‹ž‘åŠw 21Ē‹ICOE –Ē—ˆŽÐ‰ï‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJ@•―Ž18”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, pp.6-7, Mar. 2007
#2007018
’†‘šˆĀŒĐ, ũˆä‹MN, "‚ˆģ“dŒđ‚ð—p‚Ē‚―“dŒđƒmƒCƒY‚Ė’áŒļ," “Œ‹ž‘åŠw 21Ē‹ICOE –Ē—ˆŽÐ‰ï‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJ@•―Ž18”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, pp.8-9, Mar. 2007
#2007019
ŠÖ’J‹B, ‚‹{^, –ėŒû‹VW, ’†–ėT‘ū˜Y, ‰Á“Ą—Sė, ”ä’ØaŽũ, ũˆä‹MN, õ’J—ē•v, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ƃvƒ‰ƒXƒeƒBƒbƒNÚ“_ƒXƒCƒbƒ`‚ð—p‚Ē‚―ƒƒCƒ„ƒŒƒX“d—Í“`‘—ƒV[ƒg," 2007”Nt‹G‘æ54‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, _“ސė, 30a-W-8, Mar. 2007
#2007020
K. Hizu, T. Sekitani, J. Otsuki, M. Takamiya, T. Sakurai, and T. Someya, "Air-stable operation of complementary circuits on plastic film using n-type organic semiconductor molecules," ƒiƒmŒõ“dŽqƒfƒoƒCƒX‚Æ—ĘŽqî•ņƒGƒŒƒNƒgƒƒjƒNƒX, “Œ‹žƒK[ƒfƒ“ƒpƒŒƒX, pp.21, Mar. 2007
#2007021
Y. Kato, T. Sekitani, M. Takamiya, M. Doi, K. Asaka, T. Sakurai, and T. Someya, "Integration of organic semiconducting nano-materials and plastic actuators for sheet-type Braille displays," ƒiƒmŒõ“dŽqƒfƒoƒCƒX‚Æ—ĘŽqî•ņƒGƒŒƒNƒgƒƒjƒNƒX, “Œ‹žƒK[ƒfƒ“ƒpƒŒƒX, pp.20, Mar. 2007
#2007022
S. Nakano, T. Sekitani, S. Takatani, M. Takamiya, T. Sakurai, and T. Someya, "Printed Plastic Switch Array for the Application to High Power Electronics," Material Research Society (MRS) Spring Meeting, San Francisco, USA, N8.9, Apr. 2007
#2007023
T. Someya, T. Sekitani, Y. Noguchi, S. Nakano, S. Takatani, M. Takamiya, and T. Sakurai, "Printed Organic Transistors for Large-area Sensors and Actuators," Material Research Society (MRS) Spring Meeting, San Francisco, USA, O10.6, Apr. 2007
#2007024
Fayez Robert Saliba, Hiroshi Kawaguchi, and Takayasu Sakurai, "A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's," IEICE Transactions on Electronics, Vol.Vol.E90-C, No.4, pp.743-748, Apr. 2007
#2007025
Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, and Takayasu Sakurai, "An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors," IEICE Transactions on Electronics, Vol.Vol.E90-C, No.4, pp.786-792, Apr. 2007
#2007026
Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, and Tadahiro Kuroda, "Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link," IEICE Transactions on Electronics, Vol.Vol.E90-C, No.4, pp.829-835, Apr. 2007
#2007027
Tsuyoshi Sekitani, Makoto Takamiya, Yoshiaki Noguchi, Shintaro Nakano, Yusaku Kato, Takayasu Sakurai, and Takao Someya, "A large-area wireless power-transmission sheet using printed organic transistors and plastic MEMS switches," Nature Materials, Vol.6, No., pp.413-417, Apr. 2007
#2007028
Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, and Takayasu Sakurai, "Design for Mixed Circuits of Organic FETs and Plastic MEMS Switches for Wireless Power Transmission Sheet," IEEE International Conference on Integrated Circuit Design and Technology, pp.168-171, June 1, 2007
#2007029
Kohei Onizuka, Makoto Takamiya, Hiroshi Kawaguchi, and Takayasu Sakurai, "A design methodology of chip-to-chip wireless power transmission system," IEEE International Conference on Integrated Circuit Design and Technology, pp.143-146, June 1, 2007
#2007030
Yasumi Nakamura, Makoto Takamiya, and Takayasu Sakurai, "An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise," IEEE Symposium on VLSI Circuits, pp.124-125, June 2007
#2007031
Takao Someya, Takayasu Sakurai, Tsuyoshi Sekitani, and Yoshiaki Noguchi, "Printed Organic Transistors for Large-Area Electronics," 6th International Conference on Polymers and Adhesives in Microelectronics and Photonics, pp.6-11, June 2007
#2007032
Tsuyoshi Sekitani, Makoto Takamiya, Shintaro Nakano, Yoshiaki Noguchi, Yusaku Kato, Takayasu Sakurai, and Takao Someya, "Printed organic transistor circuits for a large-area wireless power transmission sheet," 3rd Annual Organic Microelectronics Workshop, Seattle, USA, July 2007
#2007033
ėŒû”Ž, ‚‹{^, ŠÖ’J‹B, ‹{–{Šėķ, –ėŒû‹VW, õ’J—ē•v, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Æ ƒvƒ‰ƒXƒ`ƒbƒNMEMSƒXƒCƒbƒ`‚ðWÏ‰ŧ‚ĩ‚―–ģü“d—Í“`‘—ƒV[ƒgŒü‚Ŋ‚Ė‰ņ˜H‹Zp," “dŽqî•ņ’ʐMŠw‰ï@MŠw‹Z•ņ, _ŒË, ICD2007-63, pp.153-158, July 2007
#2007034
ũˆä‹MN, "ƒ€[ƒA‚Ė–@‘Ĩ‚ĖŒĀŠE‚ð’ī‚Ķ‚Ä," “úŒoŽY‹ÆV•·, ”ž“ą‘Ė‘‡@L“ÁW, pp.16, Aug. 21, 2007
#2007035
’†‘šˆĀŒĐ, ‚‹{^, ũˆä‹MN, "‚ˆģ“dŒđü‚ð—p‚Ē‚―ƒIƒ“ƒ`ƒbƒv“dŒđüƒmƒCƒYƒLƒƒƒ“ƒZƒ‰," “dŽqî•ņ’ʐMŠw‰ï@MŠw‹Z•ņ, –kŒĐ, ICD2007-85, pp.91-94, Aug. 24, 2007
#2007036
ũˆä‹MN, "V•Š–ėŠJ‘ņ‚ÉŒü‚Ŋ‚ă|ƒŠƒ}[MEMS‚É’–Ú," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX, 8, pp.37, Aug. 2007
#2007037
‰Īāô, ‹S’ˍ_•―, ‚‹{^, ũˆä‹MN, "Žš“āƒ}ƒ‹ƒ`ƒIƒuƒWƒFƒNƒg‚Ė‹óŠÔ“IˆĘ’u“Ŋ’čƒVƒXƒeƒ€‚ÉŠÖ‚·‚éˆęŒŸ“Ē," “dŽqî•ņ’ʐMŠw‰ïƒGƒŒƒNƒgƒƒjƒNƒXƒ\ƒTƒCƒGƒeƒB‘å‰ï, ’đŽæ‘åŠw, C-12-30, pp.85, Sep. 12, 2007
#2007038
VŽR‘ū˜Y, –p“N, ‚‹{^, ũˆä‹MN, "ƒIƒ“ƒ`ƒbƒv‘ū—z“d’r‹ė“Ū287mV, 13.3MHzƒŠƒ“ƒOƒIƒVƒŒ[ƒ^," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, ’đŽæ‘åŠw, C-12-36, pp.91, Sep. 12, 2007
#2007039
‹{–{Šėķ, ‚‹{^, ũˆä‹MN, "UWBƒCƒ“ƒpƒ‹ƒX’ʐMŒü‚Ŋƒpƒ‹ƒXķŽ‰ņ˜H," “dŽqî•ņ’ʐMŠw‰ïƒGƒŒƒNƒgƒƒjƒNƒXƒ\ƒTƒCƒGƒeƒB‘å‰ï, ’đŽæ‘åŠw, C-12-37, pp.92, Sep. 12, 2007
#2007040
ŽüŽuˆĖ, —ŦŠyđ, ‚‹{^, ũˆä‹MN, "üŒ`Ŧ‚É—D‚ę‚―ƒfƒWƒ^ƒ‹§Œä‚ĩ‚Ŧ‚Ē“dˆģ‰Â•ÏƒRƒ“ƒpƒŒ[ƒ^," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, ’đŽæ‘åŠw, C-12-30, Sep. 12, 2007
#2007041
Takayasu Sakurai, "(Invited)Meeting with the Forthcoming IC Design-Solving issues by 3D stacking," SBCCI2007, Rio de Janeiro, Bragil, pp.2, Sep. 2007
#2007042
D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution," 33rd European Solid-State Circuits Conference (ESSCIRC), Munich, Germany, pp.190-193, Sep. 2007
#2007043
D. Levacq, T. Minakawa, M. Takamiya, and T. Sakurai, "A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 x 1 Transistor Arrays in 90nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp.257-260, Sep. 2007
#2007044
ŠÖ’J‹B, –ėŒû‹VW, ’†–ėT‘ū˜Y, ‰Á“Ą—Sė, ‚‹{^, ũˆä‹MN, õ’J—ē•v, "ˆóü‹Zp‚ð—p‚Ē‚―—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^EÚ“_ƒXƒCƒbƒ`‚Æ‘å–ĘÏƒƒCƒ„ƒŒƒX“d—Í“`‘—ƒV[ƒg," 2007”NH‹G‘æ68‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ï, ŽD–y, 8a-D-1, Sep. 2007
#2007045
Takayasu Sakurai and Takao Someya, "ƒƒCƒ„ƒŒƒX“d—Í“`‘—ƒV[ƒg," ‰ž—p•Ļ—, ‘æ76ŠŠ, ‘æ10†, pp.1159-1163, Oct. 2007
#2007046
ũˆä‹MN, "i“Á•Ęu‰‰jÝŒv‚Đ‚įŒĐ‚―3ŽŸŒģSiPƒ\ƒŠƒ…[ƒVƒ‡ƒ“," ƒGƒŒƒNƒgƒƒjƒNƒXŽĀ‘•Šw‰ïƒ[ƒNƒVƒ‡ƒbƒv, ƒ‰ƒtƒH[ƒŒC‘PŽ›, Nov. 18, 2007
#2007047
ũˆä‹MN, "iŠî’ēu‰‰jˆŲ•Š–ė˜AŒgAƒCƒmƒx[ƒVƒ‡ƒ“AĒŠE," ‘æ11‰ņƒVƒXƒeƒ€LSIƒ[ƒNƒVƒ‡ƒbƒv, –k‹ãB‘Û‰ï‹cę, Nov. 19, 2007
#2007048
D. Levacq, M. Takamiya, and T. Sakurai, "Backgate Bias Accelerator for 10ns-order Sleep-to-Active Modes Transition Time," IEEE Asian Solid-State Circuits Conference (A-SSCC), Jeju, Korea, pp.296-299, Nov. 2007
#2007049
K. Onizuka, K. Inagaki, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs," IEEE Journal of Solid-State Circuits, Vol.42, No.11, pp.2404-2410, Nov. 2007
#2007050
Hiroshi Kawaguchi, Danardono Dwi Antono, and Takayasu Sakurai, "Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines," IEICE Transactions on Electronics, Vol.Vol.E90-A, No.12, pp.2669-2681, Nov. 2007
#2007051
M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, and T. Sakurai, "(Invited) Wireless Power Transmission Sheet with Organic FETs and Plastic MEMS Switches," International Display Workshop (IDW), Sapporo, Japan, pp.95-98, Dec. 2007
#2007052
T. Sekitani, Y. Noguchi, S. Nakano, K. Zaitsu, Y. Kato, M. Takamiya, T. Sakurai, and T. Someya, "Communication Sheets Using Printed Organic Nonvolatile Memories," IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, Dec. 2007
#2007053
ũˆä‹MN, "2ŽŸŒģ‚Đ‚į3ŽŸŒģ‚Ö‚Ė“]Š·‚Å”ž“ą‘Ė‚͐V‚―‚ČƒXƒe[ƒW‚Ö," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX“Á•Ę•ŌW”Å, pp.20-21, 2007

2006

#2006001
T. Someya, T. Sekitani, and T. Sakurai, "Organic TFT-AM for Large-Area Sensors and Actuators," 2006 International Thin-Film Transistor Conference, Session 6: Emerging Technology, Kitakyushu, 6.1, Jan. 19, 2006
#2006002
‹S’ˍ_•―, ũˆä‹MN, "ƒiƒm•bƒI[ƒ_[‚ŕψډ”\‚ČƒIƒ“ƒ`ƒbƒv“dŒđ‰ņ˜HŒü‚ŊVDDƒzƒbƒsƒ“ƒOƒAƒNƒZƒ‰ƒŒ[ƒ^," “dŽqî•ņ’ʐMŠw‰ï‹Z•ņ, 105, 569, pp.13-17, Jan. 2006 (PDF)
#2006003
N. Miura, D. Mizoguchi, M. Inoue, T. Sakurai, and T. Kuroda, "A 195-Gb/s 1.2-W Inductive Inter-Chip Wireless Superconnect for 3-D-Stacked System in a Package," IEEE Journal of Solid-State Circuits (JSSC), Vol.41, No.1, pp.23-34, Jan. 2006
#2006004
S. Iba, Y. Kato, T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Use of laser drilling in the manufacture of organic inverter circuits," Analytical and Bioanalytical Chemistry, Vol.384, No.2, pp.374-377, Jan. 2006
#2006005
T. Someya, T. Sakurai, and T. Sekitani, "Recent Progress of Flexible Large-area Sensors and Actuators with Organic Transistor Integrated Circuits," COEƒ~ƒjƒ[ƒNƒVƒ‡ƒbƒvu‹­‘ŠŠÖƒGƒŒƒNƒgƒƒjƒNƒX‚Ėi“Wv, “Œ‹ž‘åŠw”ƒLƒƒƒ“ƒpƒX, Jan. 2006
#2006006
õ’J—ē•v, ŠÖ’J‹B, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ĖDCƒXƒgƒŒƒX," “Á’č—ĖˆæŒĪ‹†uV‚ĩ‚ĒŠÂ‹Ŧ‰š‚É‚Ļ‚Ŋ‚é•ŠŽqŦ“ą‘Ė‚Ė“ÁˆŲ‚Č‹@”\‚Ė’Tõv‘æ‚S‰ņƒVƒ“ƒ|ƒWƒEƒ€, Jan. 2006
#2006007
Î“cŒõˆę, ƒAƒeƒBƒbƒg ƒ^ƒ€ƒ^ƒJ[ƒ“, Î•mŠö, ũˆä‹MN, "ƒXƒP[ƒŠƒ“ƒO‚ģ‚ę‚―ƒgƒ‰ƒ“ƒWƒXƒ^‚É“K‰ž‚ĩ‚―‚‘ψģƒIƒyƒAƒ“ƒvÝŒv," ICDŒĪ‹†‰ï MŠw‹Z•ņVol. 105, pp.1-6, Jan. 2006 (PDF)
#2006008
K. Ishida, A. Tamtrakarn, and T. Sakurai, "A 0.5-V Sigma-Delta Modulator Using Analog T-Switch Scheme for the Subthreshold Leakage Suppression," 2006 IEEE Asia and South Pacific Design Automation Conference, pp.98-99, Jan. 2006 (PDF)(PDF2)
#2006009
‹T‰ŠH’j, ũˆä‹MN, “Œ“N˜Y, ’Jd—Y, "ŽY‹ÆŠE‘n‘Ē‚ÉŒü‚Ŋ‚Ä‚ĖŒø‰Ę“I‚ČŒĪ‹†@ŠJ”­‚Ė„i‚ð–ÚŽw‚·‹Zpí—Šƒ}ƒbƒv," ŒoÏŽY‹ÆƒWƒƒ[ƒiƒ‹(ŒoÏŽY‹Æ’ēļ‰ï), Feb. 1, 2006
#2006010
Œā•ķ‹, "“dŒđ“dˆģA‚ĩ‚Ŧ‚Ē’l“dˆģ‚Ė“Ū“I§Œä‚É‚æ‚éVLSI’áÁ”ï“d—͉ŧ‚ĖŒĪ‹†," CŽm˜_•ķ, Feb. 2007
#2006011
N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link," IEEE International Solid-State Circuits Conference (ISSCC'06), pp.424-425, Feb. 2006
#2006012
ũˆä‹MN, "ŽYŠw˜AŒg‚𐎌ũ‚ģ‚đ‚é‚ā‚Ī1‚‚Ė•û–@," ŠwķŒü‚Ŋ“Á•Ę•ŌW”Å –ū“ú‚ĖƒGƒ“ƒWƒjƒA‚Ö‚ĖŽčŽ† 2005 (“úŒoBPŽÐ), Feb. 2006
#2006013
M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase the Static Noise Margin," IEEE International Solid-State Circuits Conference (ISSCC'06), pp.276-277, Feb. 2006
#2006014
Y. Kato, T. Sekitani, M. Takamiya, Masao Doi, K. Asaka, T. Sakurai, and T. Someya, "Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators," IEEE Transactions on Electron Devices, Vol.54, No.2, pp.202-209, Feb. 2007
#2006015
‹T‰ŠH’j, ũˆä‹MN, “Œ“N˜Y, ’Jd—Y, "ŽY‹ÆŠE‘n‘Ē‚ÉŒü‚Ŋ‚Ä‚ĖŒø‰Ę“I‚ČŒĪ‹†@ŠJ”­‚Ė„i‚ð–ÚŽw‚·‹Zpí—Šƒ}ƒbƒv," ŒoÏŽY‹ÆƒWƒƒ[ƒiƒ‹(ŒoÏŽY‹Æ’ēļ‰ï), pp.6-15, Feb. 2006
#2006016
ŠFė‘ņ–į, "ƒiƒmƒ[ƒgƒ‹Ē‘ã‚Ė’áÁ”ï“d—ÍCMOSƒƒWƒbƒNƒ‰ƒCƒuƒ‰ƒŠ‚ĖŒĪ‹†," CŽm˜_•ķ, Feb. 2007
#2006017
Î“cŦ–į, "ƒEƒ‹ƒgƒ‰ƒƒCƒhƒoƒ“ƒh–ģü’ʐM‚É‚Þ‚Ŋ‚―’áÁ”ï“d—ÍCMOSŽóM‰ņ˜H‚ĖŒĪ‹†," CŽm˜_•ķ, Feb. 2007
#2006018
‹S’ˍ_•―, ũˆä‹MN, "’á“d—ÍVLSI‚ÅŽg—p‚ģ‚ę‚é“dŒđ‰ņ˜H‹Zp," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆ‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž17”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp.12-13, Mar. 14, 2006
#2006019
C. Q. Tran, H. Kawaguchi, and T. Sakurai, "Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating Dual-VTH/VDD and Micro-VDD-Hopping," IEICE Transactions on Electronics, Vol.E89-C, No.3, pp.280-286, Mar. 2006
#2006020
D. D. Antono, K. Inagaki, H. Kawaguchi, and T. Sakurai, "Trends of On-Chip Interconnects in Deep Sub-Micron ," IEICE Transactions on Electronics, Vol.E89-C, No.3, pp.392-394, Mar. 2006 (PDF)
#2006021
Atit Tamtrakarn and T. Sakurai, "Low-power Circuits and Architectures for Ultra-Wide-Band(UWB) Transceiver toward Ubiquitous Electronics Applications," ”ŽŽm˜_•ķ, “Œ‹ž‘åŠw, Mar. 2006
#2006022
D. D. Antono and T. Sakurai, "Modeling and Characterization of Electrical Behaviors of Interconnects in Deep Sub-micron VLSI's," ”ŽŽm˜_•ķ, “Œ‹ž‘åŠw, Mar. 2006
#2006023
C. Q. Tran and T. Sakurai, "Low-power Nano-meter CMOS Circuit Design with Application to FPGA," ”ŽŽm˜_•ķ, “Œ‹ž‘åŠw, Mar. 2006
#2006024
Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, and Tadahiro Kuroda, "A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology," IEICE Transactions on Electronics, E89-C, 3, pp.320-326, Mar. 2006
#2006025
T. Someya, T. Sakurai, and T. Sekitani, "Future Prospects of Flexible, Large-Area Sensors and Actuators with Organic Transistor ICs," 2006 VLSI-TSA conference, Taiwan, Apr. 24, 2006
#2006026
T. Someya, Y. Noguchi, Y. Kato, T. Sekitani, and T. Sakurai, "Printed organic transistors for large-area, flexible sensors and actuators," Material Research Society iMRS) Spring Meeting, Symposium L: Materials for Next-Generation Display Systems, San Francisco, Apr. 2006
#2006027
T. Someya, T. Sekitani, and T. Sakurai, "Conformable electronic artificial skins with organic transistor integrated circuits," Material Research Society iMRS) Spring Meeting, Symposium CC: Electrobiological Interfaces on Soft Substrates, San Francisco, Apr. 2006
#2006028
K. Hizu, T. Sekitani, Y. Shimada, J. Otsuki, M. Takamiya, T. Sakurai, and T. Someya, "Low voltage operation of organic CMOS inverter circuit with double-gate structure," Material Research Society iMRS) Spring Meeting, Symposium M: Conjugated Organic Materials - Synthesis, Structure, Device and Applications, San Francisco, Apr. 2006
#2006029
T. Sekitani, Y. Takamatsu, S. Nakano, T. Sakurai, and T. Someya, "Hall effect measurements using pentacene thin-film transistors on plastic films," Material Research Society iMRS) Spring Meeting, Symposium M: Conjugated Organic Materials - Synthesis, Structure, Device and Applications, San Francisco, Apr. 2006
#2006030
T. Sekitani, T. Someya, and T. Sakurai, "Effects of Annealing on Pentacene Field-Effect Transistors using Polyimide Gate Dielectric Layers," Journal of Applied Physics, Vol.100, 024513, No., Apr. 2006
#2006031
K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Managing Subthreshold Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T- Switch (AT-Switch) and Super Cut-off CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol.41, No.4, pp.859-867, Apr. 2006 (PDF)
#2006032
K. S. Min, H. D. Choi, H. Y. Choi, H. kawaguchi, and T. Sakurai, "Leakage-Suppressed Clock-Gating Circuit with Zigzag Super Cut-Off CMOS (ZSCCMOS) for Leakage-Dominant Sub70-nm and Sub-1-V-VDD LSIs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.14, No.4, pp.430-435, Apr. 2006
#2006033
õ’J—ē•v, ŠÖ’J‹B, ũˆä‹MN. , "ƒtƒŒƒLƒVƒuƒ‹ƒZƒ“ƒT[Au—L‹@Šî”ã‚Ė“dŽqƒfƒoƒCƒXv ," ƒV[ƒGƒ€ƒV[o”Å, pp.327-337, Apr. 2006
#2006034
ŠÖ’J‹B, ũˆä‹MN, õ’J—ē•v, "—L‹@Œ‹ŧ”––Œ‚ð—p‚Ē‚―WÏ‰ņ˜H," ‰ž—p•Ļ—Šw‰ïŒ‹ŧHŠw•Š‰Č‰ïŽåÃ ‘æ124‰ņŒ‹ŧHŠw•Š‰Č‰ïŒĪ‹†‰ï, Apr. 2006
#2006035
T. Someya, T. Sekitani, and T. Sakurai, "Printed organic transistors for large-area electronics," The 6th International Meeting on Information Display and the International Display Manufacturing Conference (IMID/IDMC 2006), Display Electronics & System, Exhibition & Convention Center (EXCO) in Daegu, Korea, May 8, 2006
#2006036
T. Someya, T. Sekitani, and T. Sakurai, "Conformable, lightweight, large-area sheet-type sensors with organic transistor integrated circuits," Symposium Q: Chem & Bio Sensing Transistors: from Materials to Systems, The European Materials Research Society (E-MRS 2006) Spring Meeting, Acropolis Congress Center, Nice, France, May 2006
#2006037
ũˆä‹MN, "ŽYŠw˜AŒg‚Ė“–Ž–ŽŌ‚Ė—§ę‚Đ‚įAŠî‘bŒĪ‹†‚ĖŽ‰Ę‚ðŽĀ—p‚É“WŠJ‚·‚éŽd‘g‚Ý‚Ė‚ ‚é‚Ũ‚ŦŽp," ƒpƒVƒtƒBƒR‰Ą•l@‰ï‹cƒZƒ“ƒ^[3F‘å‰ï‹cŽš, May 2006
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M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators," IEEE International Conference on IC Design and Technology (ICICDT), Padova, Italy, pp.219-222, May 2006
#2006039
T. Someya, T. Sakurai, and T. Sekitani, "Recent progress of organic TFT active matrices for large-area electronics applications," International Congress of Imaging Science: ICIS'06, Rochester, New York, May 2006
#2006040
ŽO‰Y“T”V, aŒû‘å‰î, ˆäãáÁ—œ, V’à ˆĻˆę, ’†ėŒđ—m, “cŽq‰ëŠî, [Î@ķ, ũˆä‹MN, •“c’‰L, "1Tb/s 3W ƒ`ƒbƒvŠÔ—U“ąŒ‹‡ƒNƒƒbƒNƒf[ƒ^ƒgƒ‰ƒ“ƒV[ƒo," “dŽqî•ņ’ʐMŠw‰ï‹Z•ņ, 106, 71, pp.95-100, May 2006
#2006041
ėŒû”Ž, ‚‹{^, ŠÖ’J‹B, ‰Á“Ą—Sė, õ’J—ē•v, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ƃvƒ‰ƒXƒ`ƒbƒNƒAƒNƒ`ƒ…ƒG[ƒ^‚ðWÏ‰ŧ‚ĩ‚―ƒtƒŒƒLƒVƒuƒ‹‚Č“_ŽšƒfƒBƒXƒvƒŒƒCŒü‚Ŋ‚Ė‰ņ˜H‹Zp," “dŽqî•ņ’ʐMŠw‰ï‹Z•ņ, ICD2006-22, pp.1-6, May 2006
#2006042
–ėŒû‹VW, ŠÖ’J‹B, ũˆä‹MN, õ’J—ē•v, "ˆóüƒvƒƒZƒX‚ð—˜—p‚ĩ‚―—L‹@“dŠEŒø‰Ęƒgƒ‰ƒ“ƒWƒXƒ^‚Ėėŧ," ƒiƒmŒõE“dŽqƒfƒoƒCƒXƒVƒ“ƒ|ƒWƒEƒ€@`—ĘŽqƒhƒbƒg‚ƃtƒHƒgƒjƒbƒNŒ‹ŧ`, “Œ‹ž@Žl’J@Žå•w‰ïŠŲƒvƒ‰ƒUƒGƒt, May 2006
#2006043
T. Sekitani, Y. Kato. K, Asaka, Masao Doi, M. Takamiya, T. Sakurai, and T. Someya, "Integration of Soft Actuators with Organic Transistor Integrated Circuits for Sheet-type Braille Displays," ƒiƒmƒeƒN‚ƃoƒCƒI‚Ė—Z‡ŒĪ‹†\lH‹Ø“ũŠJ”­‚Ė“W–](‘æ‚R‰ņlH‹Ø“ũƒRƒ“ƒtƒ@ƒŒƒ“ƒX), “Œ‹žH—tŒīƒRƒ“ƒxƒ“ƒVƒ‡ƒ“ƒZƒ“ƒ^[, May 2006
#2006044
õ’J—ē•v, ŠÖ’J‹B, –ėŒû‹VW, ’†–ėT‘ū˜Y, ũˆä‹MN , "‹ā‘Ūƒiƒm—ąŽq‚ĖƒCƒ“ƒNƒWƒFƒbƒgˆóü‚Æ—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ö‚Ė‰ž—p," ƒiƒmŒõE“dŽqƒfƒoƒCƒXƒVƒ“ƒ|ƒWƒEƒ€@`—ĘŽqƒhƒbƒg‚ƃtƒHƒgƒjƒbƒNŒ‹ŧ`, “Œ‹žŽl’J, May 2006
#2006045
M. Inoue, N. Miura, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link," IEEE Symposium on VLSI Circuits, 8.3, pp.80-81, June 15, 2006 (PDF)
#2006046
K. Inagaki, D. Antono, M. Takamiya, S. Kumashiro, and T. Sakurai, "A 1-ps Resolution On-chip Sampling Oscilloscope with 64:1 Tunable Sampling Range Based on Ramp Waveform Division Scheme," IEEE Symposium on VLSI Circuits, 8.1, pp.76-77, June 15, 2006 (PDF)
#2006047
T. Sekitani, Shingo Iba, Y. Kato, Y. Noguchi, T. Sakurai, and T. Someya, "Submillimeter radius bendable organic field-effect transistors," JOURNAL OF NON-CRYSTALLINE SOLIDS, Vol.352, No., pp.1769-1773, June 15, 2006
#2006048
A. Tamtrakarn, H. Ishikuro, K. Ishida, M. Takamiya, and T. Sakurai, "A 1-V 299ƒĘW Flashing UWB Transceiver Based on Double Thresholding Scheme," IEEE Symposium on VLSI Circuits, 23.2, pp.250-251, June 17, 2006
#2006049
T. Someya, T. Sakurai, and T. Sekitani, "Large-area Electronics Based on Organic Transistors," 64th Device Research Conference (DRC), Penn State University, June 28, 2006
#2006050
T. Sakurai, "Short Course on Optimal Interconnect Design - A Systems Perspestive," IEEE International Interconnect Technology Conference (IITC), Hyatt Regency at San Francisco Airport, June 2006
#2006051
T. Sekitani, Y. Takamatsu, S. Nakano, T. Sakurai, and T. Someya, "Hall effect measurements using polycrystalline pentacene field-effect transistors on plastic films," Applied Physics Letters, Vol.88(25), No.Art. No. 253508, June 2006
#2006052
ũˆä‹MN, "WÏ‰ņ˜H‚ĖÅæ’[‚Æ–Ē—ˆ," ‘æ33‰ņƒCƒuƒjƒ“ƒOƒZƒ~ƒi[, “Œ‹ž‘åŠwķŽY‹ZpŒĪ‹†Š, June 2006
#2006053
ũˆä‹MN, "STARC‚Ö‚ĖƒƒbƒZ[ƒW," ‚ ‚·‚Đ‚ÆAS™PLA, ”ž“ą‘Ė—HŠwŒĪ‹†ƒZƒ“ƒ^[, June 2006
#2006054
T. Someya, T. Sakurai, and T. Sekitani, "Flexible, Large-Area Sensors and Actuators using Organic Transistor Integrated Circuits," 2006 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices (AWAD2006), Tohoku University, July 3, 2006
#2006055
T. Someya, T. Sakurai, and T. Sekitani, "Large-area Electronics Based on Organic Transistor ICs," 2nd Annual Organic Microelectronics Workshop, Tronto, July 9, 2006
#2006056
N. Miura, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "A 1Tb/s 3W Inductive-Coupling Transceiver for 3D ICs," 2006 Intenational PhD Workshop on SoC (IPS), July 2006
#2006057
ũˆä‹MN, "”ž“ą‘ĖWÏ‰ņ˜H‚Ė‰Û‘č‚Æ“W–]," ‘æ29‰ņƒAƒhƒoƒ“ƒeƒXƒg‹Zp”­•\‰ï, ƒAƒhƒoƒ“ƒeƒXƒg ŒQ”nR&DƒZƒ“ƒ^, July 2006
#2006058
T. Sekitani, Y. Noguchi, T. Sakurai, and T. Someya, "Inkjet Printing of 33 cm Organic Field-Effect Transistor Active Matrices for the Application to Electronic Artificial Skins," 2006 The International Conference on Science and Technology of Synthetic Metals (ICSM2006), Trinity College Dublin in Ireland, July 2006
#2006059
T. Someya, T. Sakurai, and T. Sekitani , "Flexible, Large-Area Electronics Using Organic Transistors," 25th Electronic Materials Symposium, Session G: Organic Electronics, ƒzƒeƒ‹ƒTƒ“ƒoƒŒ[•xŽmŒĐ, July 2006
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”ä’ØaŽũ, ŠÖ’J‹B, “‡“c‚æ‚ĪŽq, ‘匎õ, ‚‹{^, ũˆä‹MN, õ’J—ē•v, "ƒ_ƒuƒ‹ƒQ[ƒg\‘Ē‚É‚æ‚é—L‹@CMOS‰ņ˜H‚Ė’á“dˆģ‹ė“Ū," —L‹@ƒGƒŒƒNƒgƒƒjƒNƒX(OME)ŒĪ‹†‰ï, #7, July 2006
#2006061
ũˆä‹MN, "WÏ‰ņ˜H‚Ė‰Û‘č‚Æ–Ē—ˆ," •―Ž18”N“xW’†u‹` ‹ÉŒĀ’m”\ƒfƒoƒCƒXHŠw, pp.33-58, July 2006
#2006062
ˆîŠ_ŒŦˆę, ƒ_ƒiƒ‹ƒhƒm ƒhƒDƒC ƒAƒ“ƒgƒm, ‚‹{^, ŒF‘㐎F, ũˆä‹MN, "ƒ‰ƒ“ƒv”gŒ`•ŠŠ„•ûŽŪ‚ð—p‚Ē‚―ƒIƒ“ƒ`ƒbƒvƒTƒ“ƒvƒŠƒ“ƒOƒIƒVƒƒXƒR[ƒv," “dŽqî•ņ’ʐMŠw‰ï‹Z•ņ, 106, 206, pp.25-30, Aug. 2006 (PDF)
#2006063
”ä’ØaŽũ, ŠÖ’J‹B, ‘匎õ, ũˆä‹MN, õ’J—ē•v, "‹ā‘Ū/—L‹@••Ž~–Œ‚É‚æ‚éNŒ^—L‹@“dŠEŒø‰Ęƒgƒ‰ƒ“ƒWƒXƒ^‚Ė‘å‹CˆĀ’čŦŒüã," H‹G ‘æ67‰ņ‰ž—p•Ļ—ŠwŠwpu‰‰‰ï 10.9 “Á’čƒe[ƒ}A: —L‹@ƒgƒ‰ƒ“ƒWƒXƒ^[, Aug. 2006
#2006064
Y. Takamatsu, T. Sekitani, S. Nakano, T. Sakurai, and T. Someya, "ƒvƒ‰ƒXƒeƒBƒbƒNŠî”ã‚ɍėŧ‚ģ‚ę‚―‘―Œ‹ŧƒyƒ“ƒ^ƒZƒ“FET‚Ėƒz[ƒ‹ˆÚ“Ū“x‚Æ‚ŧ‚Ė‰·“xˆË‘ķŦiTemperature dependence of Hall mobility using organic FETs manufactured on plastic filmsj," H‹G ‘æ67‰ņ‰ž—p•Ļ—ŠwŠwpu‰‰‰ï 10.9 “Á’čƒe[ƒ}A: —L‹@ƒgƒ‰ƒ“ƒWƒXƒ^[, Aug. 2006
#2006065
ŠÖ’J‹B, ‚‹{^, ũˆä‹MN, õ’J—ē•v, "—L‹@/‹ā‘Ū••Ž~–Œ‚ð—p‚Ē‚―ƒyƒ“ƒ^ƒZƒ“”––Œƒgƒ‰ƒ“ƒWƒXƒ^‚Ė‘å‹CˆĀ’čŦ," H‹G ‘æ67‰ņ‰ž—p•Ļ—ŠwŠwpu‰‰‰ï 10.9 “Á’čƒe[ƒ}A: —L‹@ƒgƒ‰ƒ“ƒWƒXƒ^[, Aug. 2006
#2006066
–ėŒû‹VW, ŠÖ’J‹B, ’†–ėT‘ū˜Y, ũˆä‹MN, õ’J—ē•v, "ˆóüƒvƒƒZƒX‚É‚æ‚é‘å–ĘÏƒZƒ“ƒT[—p‚Ė—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^ƒ}ƒgƒŠƒbƒNƒX," H‹G ‘æ67‰ņ‰ž—p•Ļ—ŠwŠwpu‰‰‰ï 10.9 “Á’čƒe[ƒ}A: —L‹@ƒgƒ‰ƒ“ƒWƒXƒ^[, Aug. 2006
#2006067
ˆäãáÁ—œ, ŽO‰Y“T”V, V’ÈĻˆę, ’†ėŒđ—m, “cŽq‰ëŠî, [Î@ķ, ũˆä‹MN, •“c’‰L, "—U“ąŒ‹‡Œ^ƒ`ƒbƒvŠÔ–ģü’ʐM‚É‚Ļ‚Ŋ‚é’áÁ”ï“d—̓fƒCƒW[ƒ`ƒF[ƒ“‘—MŠí," “dŽqî•ņ’ʐMŠw‰ï‹Z•ņ, ICD2006-79`108, 207, pp.63-68, Aug. 2006
#2006068
‚‹{^, ƒA[ƒeƒBƒbƒg ƒ^ƒ€ƒ^ƒJ[ƒ“, Î•mŠö, Î“cŒõˆę, ũˆä‹MN, "Double Thresholding Scheme‚ð—p‚Ē‚―1V 299uW Flashing UWBƒgƒ‰ƒ“ƒV[ƒo," “dŽqî•ņ’ʐMŠw‰ï‹Z•ņ, ICD2006-89, pp.57-61, Aug. 2006
#2006069
Y. Takamatsu, T. Sekitani, S. Nakano, T. Sakurai, and T. Someya, "Hall effect of polycrystalline pentacene field-effect transistors on plastic films," International Conference on Solid State Devices and Materials (SSDM), Organic Materials Science, Device Physics and Applications, Yokohama, Sep. 11, 2006
#2006070
Ņ—˜–Ŋ, ũˆä‹MN, "ƒNƒƒbƒNƒQ[ƒeƒBƒ“ƒO‚ð—p‚Ē‚―ƒpƒ[ƒQ[ƒeƒBƒ“ƒO," “dŽqî•ņ’ʐMŠw‰ïƒGƒŒƒNƒgƒƒjƒNƒXƒ\ƒTƒCƒGƒeƒB‘å‰ï, ‹ā‘ō‘åŠw, A-03-011, Sep. 21, 2006 (PDF)
#2006071
Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, and Takayasu Sakurai , "Compact outside-rail circuit structure by single-cascode two-transistor topology ," IEEE Custom Integrated Circuits Conference (CICC), pp.619-622, Sep. 2006
#2006072
K. Onizuka, H. Kawaguchi, M. Takamiya, T. Kuroda, and T. Sakurai, "Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications," IEEE Custom Integrated Circuits Conference, 15.1, pp.575-578, Sep. 2006 (PDF)
#2006073
ũˆä‹MN, "”ž“ą‘ĖƒCƒmƒx[ƒVƒ‡ƒ“—§‘‚Ö‚Ė“đ," STARCƒVƒ“ƒ|ƒWƒEƒ€2006, V‰Ą•l‘Ûƒzƒeƒ‹, Sep. 2006
#2006074
T. Sakurai, "Challenges for THE e-life at 2nd A-SSCC," IEEE Solid-state Circuits Society Newsletter, 20, 3, pp.51, Sep. 2006
#2006075
Œā•ķ‹, ‚‹{^, ũˆä‹MN, "’áÁ”ï“d—ÍVLSI ŽĀŒŧ‚ÉŒü‚Ŋ‚―“dŒđ“dˆģ‚ƊoƒCƒAƒX‚Ė“Ū“I§ŒäƒAƒ‹ƒSƒŠƒYƒ€," “dŽqî•ņ’ʐMŠw‰ïƒGƒŒƒNƒgƒƒjƒNƒXƒ\ƒTƒCƒGƒeƒB‘å‰ï, ‹ā‘ō‘åŠw, C-12-33, Sep. 2006
#2006076
Î“cŦ–į, ‚‹{^, ũˆä‹MN, "”ņ“ŊŠúƒTƒ“ƒvƒŠƒ“ƒOŒ^UWBŽóM•ûŽŪ," “dŽqî•ņ’ʐMŠw‰ïƒGƒŒƒNƒgƒƒjƒNƒXƒ\ƒTƒCƒGƒeƒB‘å‰ï, ‹ā‘ō‘åŠw, C-12-39, pp.100, Sep. 2006 (PDF)
#2006077
T. Sekitani, Y. Takamatsu, T. Sakurai, and T. Someya, "Strain and Hall Effects of Pentacence TFTs on Plastic Films," KINKEN Workshop on Organic Field Effect Transistor, Institute for Materials Research, Oct. 2006
#2006078
Y. Noguchi, T. Sekitani, T. Sakurai, and T. Someya, "ROBOT SKINS USING INKJETTED ORGANIC TRANSISTOR ACTIVE MATRICES," Korea-Japan Joint Forum (KJF) 2006 -Organic Materials for Electronics and Photonics-, Organic Display and Transistors, TOKI MESSE, Niigata Convention Center, Oct. 2006
#2006079
T. Someya, T. Sakurai, and T. Sekitani, "Recent Progress of Flexible, Large-area Sensors and Actuators with Organic Transistor Integrated Circuits," KINKEN Workshop on Organic Field Effect Transistor, Institute for Materials Research , Oct. 2006
#2006080
H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T. Someya, and T. Sakurai, "A 3D-Stack Organic Sheet-Type Scanner with Double-Wordline and Double-Bitline Structure," IEEE Sensors Journal, Vol.6, No.5, pp.1209-1217, Oct. 2006
#2006081
ũˆä‹MN, "”ž“ą‘ĖWÏ‰ņ˜H‚Ė‰Û‘č‚Æ“W–]," ƒAƒhƒoƒ“ƒeƒXƒgEƒeƒNƒjƒJƒ‹EƒŒƒ|[ƒg(Probro@27), Oct. 2006
#2006082
T. Sekitani and T. Someya, "Air-stable operation of pentacene field-effect transistors on plastic films using organic/metal hybrid passivation layers," The 2006 International Symposium on Flexible Electronics and Display (ISFED), Taiwan, Nov. 2006
#2006083
K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "VDD-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time," IEEE Journal of Solid-State Circuits, Vol.41, No.11, pp.2382-2389, Nov. 2006 (PDF)
#2006084
T. Sakurai and M. Ikeda, "Introduction to the Special Issue on the 2005 Asian Solid-State Circuits Conference(A-SSCC'05)," IEEE Journal of Solid-State Circuits, Vol.41, No.11, pp.2364-2365, Nov. 2006
#2006085
K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Stacked-chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems," IEEE Asian Solid-State Circuits Conference, pp.127-130, Nov. 2006 (PDF)
#2006086
, "‰Æ“dŧ•iAƒR[ƒh‚Ē‚į‚ļE°‚â•Į‚É“d—Í“`‘—ƒV[ƒgA“Œ‘å‚ŠŠJ”­," “ú–{ŒoÏV•·, Dec. 4, 2006
#2006087
, "“dŒđƒR[ƒh‚Ē‚į‚Č‚Ē‰Æ“d‚ŠŽĀŒŧH“Œ‘å‚Š“d—̓V[ƒgŠJ”­," “Į”„V•·, Dec. 4, 2006
#2006088
, "“d‹Cŧ•i‚ɃƒCƒ„ƒŒƒX‚Å“d—Í‹Ÿ‹‹A“Œ‘åŒĪ‹†ƒ`[ƒ€‚ŠŠJ”­," “Į”„V•·, Dec. 4, 2006
#2006089
, "“dŒđƒR[ƒh‚ā‚Í‚â•s—v ”ņÚG‚Å“d—Í‘—‚ę‚éƒV[ƒgŠJ”­," ŽYŒoV•·, Dec. 4, 2006
#2006090
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é ƒRƒ“ƒZƒ“ƒg‚Š•s—v‚ɁH," ž“ú–{E–kŠC“đE‹ž“sE•ŸˆäV•·, Dec. 4, 2006
#2006091
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é," “úŠ§•ŸˆäEē‰ęV•·, Dec. 4, 2006
#2006092
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é ƒRƒ“ƒZƒ“ƒg‚Š•s—v‚ɁH," H“cŠ@V•ņ, Dec. 4, 2006
#2006093
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é," •Ÿ“‡–Ŋ—FV•·, Dec. 4, 2006
#2006094
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é ƒRƒ“ƒZƒ“ƒg‚Š•s—v‚ɁH ," ‰Í–kV•ņ, Dec. 4, 2006
#2006095
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é^ƒRƒ“ƒZƒ“ƒg‚Š•s—v‚ɁH ," Žl‘E_ŒËE“ŋ“‡E’†‘V•·, ŽR‰A’†‰›V•ņ, Dec. 4, 2006
#2006096
, "“dŒđƒR[ƒh‚Ē‚į‚ļu“dŒđƒV[ƒgvŠJ”­ “Œ‘å," ’Đ“úV•·, Dec. 4, 2006
#2006097
ũˆä‹MN, õ’J—ē•v, "”ž“ą‘Ė‚Ė‹ß–Ē—ˆAŽOŽŸŒģ‰ŧ‚ŐV‚―‚Č—Ėˆæ‚Ö," “úŒoŽY‹ÆV•·, Dec. 4, 2006
#2006098
M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai. , "Flexible Braille Sheet Display with Organic FETs and Plastic Actuators," International Display Workshop (IDW), Otsu, Dec. 8, 2006
#2006099
”ä’ØaŽũ, ŠÖ’J‹B, ‘匎õ, ‚‹{^, ũˆä‹MN, õ’J—ē•v, "—L‹@CMOS˜_—‰ņ˜H‚ĖAC“ÁŦ," —L‹@ƒGƒŒƒNƒgƒƒjƒNƒX(OME)ŒĪ‹†‰ï, ‹@‰ïU‹ŧ‰ïŠŲ, Dec. 2006
#2006100
T. Sekitani, M. Takamiya, Y. Noguchi, S. Nakano, Y. Kato, K. Hizu, H. Kawaguchi, T. Sakurai, and T. Someya, "A Large-Area Flexible Wireless Power Transmission Sheet Using Printed Plastic MEMS Switches and Organic Field-Effect Transistors," 2006@IEEE International Electron Devices Meeting (IEDM2006), San Francisco, Dec. 2006
#2006101
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é ," “Œ‹žV•·, Dec. 2006
#2006102
, "“dŒđƒR[ƒh‚Š‚Č‚­‚Ä‚ā‘—“d “Œ‘å‚Ėũˆä‹ģŽö‚į‚ŠŠJ”­," ’†“úV•·, Dec. 2006
#2006103
, "“Œ‘åAƒR[ƒh‚Č‚ĩ‚Å‚ā“d—Í‘—‚ę‚éƒV[ƒgŠJ”­ ," ƒXƒ}[ƒgƒE[ƒ}ƒ“, Dec. 2006
#2006104
, "G‚į‚Č‚­‚Ä‚ā“d—Í‘—‚ę‚é," “Œ‰œ“ú•ņ, Dec. 2006
#2006105
T. Kuroda and T. Sakurai, "Leakage in nanometer CMOS technologies (Chapter 5: Body Biasing)," Springer, pp.105-140, 2006
#2006106
K. Usami and T. Sakurai, "Leakage in nanometer CMOS technologies (Chapter 4: Methodologies for Power Gating)," Springer, pp.77-104, 2006
#2006107
T. Someya, T. Sekitani, S. Iba, Y. Kato, T. Sakurai, and H. Kawaguchi, "Organic transistor integrated circuits for large-area sensors," MOLECULAR CRYSTALS AND LIQUID CRYSTALS, Vol., No., pp.13-22, 2006
#2006108
Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, and Takayasu Sakurai, "Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's ," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E89-A, 12, pp.3569-3578 , 2006 (PDF)
#2006109
D.D. Antono and T.Sakurai, "Modeling and Characterization of Electrical Behaviors of Interconnects in Deep Sub-micron VLSI's," •―Ž17”N“x “Œ‹ž‘åŠw ŒÅ‘ĖƒGƒŒƒNƒgƒƒjƒNƒXEƒIƒvƒgƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†”­•\‰ï, “Œ‹ž‘åŠw, 2006
#2006110
–ėŒû‹VW, ŠÖ’J‹B, •Ÿ“cŒ›“ņ˜Y, ’|ƒm‰šŒŦ“ņ, ‰Á“Ą—Sė, Ũ’Jˆę—Y, ž—t—Šd, ũˆä‹MN, õ’J—ē•v, "’ቷÄŽŒ^‹âƒiƒm—ąŽq‚ĖƒCƒ“ƒNƒWƒFƒbƒg“h•z‚Æ—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ö‚Ė‰ž—p," 2006”N(•―Ž18”N)t‹G ‘æ53‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, 26a-ZG-1, 2006
#2006111
”ä’ØaŽũ, ŠÖ’J‹B, “‡“c‚æ‚ĪŽq, ‘匎õ, ‚‹{^, ũˆä‹MN, õ’J—ē•v, "ƒ_ƒuƒ‹ƒQ[ƒg\‘Ē‚ð—p‚Ē‚―—L‹@CMOS ƒCƒ“ƒo[ƒ^‰ņ˜H‚Ė’á“dˆģ‹ė“Ū," 2006”N(•―Ž18”N)t‹G ‘æ54‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, 26a-ZG-8, 2006
#2006112
ŠÖ’J‹B, ‚ž‘ŨŽi, ’†–ėT‘ū˜Y, ũˆä‹MN, õ’J—ē•v, "ƒ|ƒŠƒCƒ~ƒh‚ðƒQ[ƒgâ‰–Œ‚É—p‚Ē‚―ƒyƒ“ƒ^ƒZƒ“”––Œƒgƒ‰ƒ“ƒWƒXƒ^‚ĖƒLƒƒƒŠƒA–§“x," 2006”N(•―Ž18”N)t‹G ‘æ55‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, 2006
#2006113
‰Á“Ą—Sė, ŠÖ’J‹B, •Ÿ“cŒ›“ņ˜Y, “yˆäģ’j, ˆĀÏ‹ÓŽu, ‚‹{^, ũˆä‹MN, õ’J—ē•v, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ƍ‚•ŠŽqƒAƒNƒ`ƒ…ƒG[ƒ^‚ĖWÏ‰ŧFƒV[ƒgŒ^“_ŽšƒfƒBƒXƒvƒŒƒC‚Ö‚Ė‰ž—p," 2006”N(•―Ž18”N)t‹G ‘æ56‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, 2006

2005

#2005001
õ’J—ē•v, ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ėŒû”Ž, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Æ—L‹@ƒ_ƒCƒI[ƒhŒõŒŸoŠí‚ĖWÏ‰ŧ," “Á’č—ĖˆæŒĪ‹†uV‚ĩ‚ĒŠÂ‹Ŧ‰š‚É‚Ļ‚Ŋ‚é•ŠŽq Ŧ“ą‘Ė‚Ė“ÁˆŲ‚Č‹@”\‚Ė’Tõv‘æ3‰ņƒVƒ“ƒ|ƒWƒEƒ€, ‹ž“s‘åŠw, Jan. 17, 2005
#2005002
õ’J—ē•v, ũˆä‹MN, ŠÖ’J‹B, ėŒû”Ž, "•ŠŽqŦƒiƒmÞ—ŋ‚ĖƒZƒ“ƒT[‰ž—p`—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ė”ũŨ‰ŧ‚ƏWÏ‰ŧ‹Zp`," u—ĘŽqƒhƒbƒgƒvƒƒWƒFƒNƒgvŒĪ‹†‰ï, “Œ‹ž‘åŠw@æ’[‰ČŠw‹ZpŒĪ‹†ƒZƒ“ƒ^[, Jan. 19, 2005
#2005003
õ’J—ē•v, ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ėŒû”Ž, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‚Æ‘å–ĘÏƒGƒŒƒNƒgƒƒjƒNƒX," •―Ž16”N“x‘æ11‰ņÞ—ŋ‰ČŠwŒĪ‹†‰ČƒZƒ~ƒi[, –k—Īæ’[‰ČŠw‹Zp‘åŠw‰@‘åŠw, Jan. 25, 2005
#2005004
H. Kawaguchi, T. Someya, T. Sekitani, and T. Sakurai, "Cut-and-Paste Customization of Organic FET Integrated Circuit and Its Application to Electronic Artificial Skin," IEEE Journal of Solid State Circuits, pp.177-185, Jan. 2005 (PDF)
#2005005
‹S’ˍ_•―, ũˆä‹MN, "’á“d—ÍVLSI‚ÅŽg—p‚ģ‚ę‚éƒIƒ“ƒ`ƒbƒv“dŒđ‰ņ˜H‚ĖŒĪ‹† ," CŽm˜_•ķ, “Œ‹ž‘åŠw, Jan. 2005
#2005006
“ŋ‰i˜aG, ũˆä‹MN, "Multi-VDD, Multi-VTH, ƒTƒCƒWƒ“‚ðŽg‚Á‚―ƒŠ[ƒN“d—ÍŽx”zĒ‘ã‚Ė’á“d—̓Xƒ^ƒ“ƒ_[ƒhƒZƒ‹ƒ‰ƒCƒuƒ‰ƒŠ‚ÉŠÖ‚·‚éŒĪ‹†," CŽm˜_•ķ, “Œ‹ž‘åŠw, Jan. 2005
#2005007
‹–@Œuá, ũˆä‹MN, "Research on Block Level Dynamic Approaches@for Low Power in Deep Sub-Micron VLSI Circuit," CŽm˜_•ķ, “Œ‹ž‘åŠw, Jan. 2005
#2005008
Î“cŒõˆę, ũˆä‹MN, "ƒ†ƒrƒLƒ^ƒXEƒGƒŒƒNƒgƒƒjƒNƒX‚ÉŒü‚Ŋ‚―’á“dˆģCMOSƒAƒiƒƒOWÏ‰ņ˜H‚ÉŠÖ‚·‚éŒĪ‹†," ”ŽŽm˜_•ķ, “Œ‹ž‘åŠw, Jan. 2005
#2005009
T. Sekitani, Y. Kato, S. Iba, H. Shinaoka, T. Someya, T. Sakurai, and S. Takagi, "Bending experiment on pentacene field-effect transistors on plastic films," Applied Physics Letters vol. , 86, pp.073511, Feb. 14, 2005
#2005010
õ’J—ē•v, ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ėŒû”Ž, ũˆä‹MN, "ˆóü–@‚ōė‚éˆģ—̓Zƒ“ƒT," ‚•ŠŽqŠw‰ïu‰‰‰ï, 2005”N“xˆóüEî•ņ‹L˜^E•\ŽĶŒĪ‹†‰ïuĀu•\ŽĶE‹L˜^‹Zp‚ðŽx‚Ķ‚éÞ—ŋ‚ƃvƒƒZƒX‚ĖV“WŠJ, ”­–ū‰ïŠŲƒz[ƒ‹, Feb. 17, 2005
#2005011
Î“cŒõˆę, ũˆä‹MN, "ƒ†ƒrƒLƒ^ƒXEƒGƒŒƒNƒgƒƒjƒNƒX‚ÉŒü‚Ŋ‚―’á“dˆģCMOSƒAƒiƒƒOWÏ‰ņ˜H‚ÉŠÖ‚·‚éŒĪ‹†," •―Ž16”N“x “Œ‹ž‘åŠw ŒÅ‘ĖƒGƒŒƒNƒgƒƒjƒNƒXEƒIƒvƒgƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†”­•\‰ï, “Œ‹ž‘åŠw, pp.75-80, Feb. 28, 2005
#2005012
N. Miura, D. Mizoguchi, M. Inoue, H. Tsuji, T. Sakurai, and T. Kuroda, "A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme," IEEE International Solid-State Circuits Conference (ISSCC'05), Dig. Tech. Papers, San Francisco, pp.pp.264-265, Feb. 2005 (PDF)
#2005013
H. Kawaguchi, Y. Shin, and T. Sakurai, "ƒĘITRON-LP: Power-Conscious Real-Time OS Based on Cooperative Voltage Scaling for Multimedia Applications," IEEE Transaction on Multimedia, 7, pp.67-74, Feb. 2005 (PDF)
#2005014
H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T. Someya, and T. Sakurai, "A Sheet-Type Scanner Based on a 3D-Stacked Organic-Transistor Circuit Using Double Word-Line and Bit-Line Structure," IEEE International Solid-State Circuits Conference Digest of Technical Papers, 32.3, pp.580-581, Feb. 2005 (PDF)
#2005015
S. Iba, T. Sekitani, Y. Kato, T. Sakurai, and T. Someya, "Lowering Operation Voltage of Pentacene Field-effect Transistors with Polyimide Gate Dielectric Layers," 3P-C22, Third International Conference on Molecular Electronics and Bioelectronics (M&BE3), National Center of Sciences, Tokyo, Mar. 3, 2005
#2005016
Y. Kato, T. Sekitani, S. Iba, T. Sakurai, and T. Someya, "Manufacturing Process and Characterization of Organic Diode-based Sheet Thermal Sensors," 4O-A09, Third International Conference on Molecular Electronics and Bioelectronics (M&BE3), National Center of Sciences (National Institute of Informatics), Tokyo, Mar. 3, 2005
#2005017
ˆÉ’ëMŒá, ‰Á“Ą—Sė, ŠÖ’J‹B, ėŒû”Ž, ũˆä‹MN, õ’J—ē•v, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Æ—L‹@ŒõƒZƒ“ƒT[‚ĖWÏ‰ŧ‚ƃV[ƒgŒ^ƒCƒ[ƒWƒXƒLƒƒƒi[‚Ö‚Ė‰ž—p," —L‹@ƒfƒBƒXƒvƒŒƒC/—L‹@ƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†‰ïu•\ŽĶ‹L˜^—p—L‹@Þ—ŋ‹y‚ŅƒfƒoƒCƒXEˆę”ʁv, ‹@ŠBU‹ŧ‰ïŠŲ, Mar. 3, 2005
#2005018
õ’J—ē•v, ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ũˆä‹MN, ėŒû”Ž, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‹Zp‚Æ“dŽqlH”į•†ƒV[ƒg," ‘æ32‰ņƒjƒ…[ƒZƒ‰ƒ~ƒbƒNƒXƒZƒ~ƒi[, V‘åãƒVƒeƒBƒvƒ‰ƒU, Mar. 4, 2005
#2005019
T. Sekitani, S. Iba, Y. Kato, T. Sakurai, and T. Someya,, "Thermal Tolerance of Encapsulated Organic Field-Effect Transistors on Plastic Films," International Symposium on Quantum Dots and Photonic Crystals 2005, Toranomon Pastoral, Toranmon, , `‹æ, Mar. 7, 2005
#2005020
T. Sakurai, "ƒAƒ“ƒrƒGƒ“ƒgEƒGƒŒƒNƒgƒƒjƒNƒX‚Æ‚ŧ‚ĖƒL[EƒeƒNƒmƒƒW[," NECƒeƒNƒmƒƒW[ƒtƒH[ƒ‰ƒ€, pp.323-341, Mar. 15, 2005
#2005021
Atit Tamtrakarn and T, Sakurai, "3.1-5GHz ultra-wideband architecture and low-power design methodology," “dŽqî•ņ’ʐMŠw‰ï@‘‡‘å‰ï, Mar. 22, 2005
#2005022
Y. Kato, T. Sekitani, S. Iba, T. Sakurai, and T. Someya, "Temperature Dependence of I-V Characteristics of Organic PN Diodes and Their Application to Sheet Thermal Sensors, H2.9, Material Research Society Spring Meeting, Symposium H," Giant-Area Electronics on Nonconventional Substrates, Mar. 31, 2005
#2005023
Danardono Dwi Antono, ũˆä‹MN, "On-chip Digital Oscilloscope for Signal Integrity Study," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆ‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž16”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp.10-11, Mar. 2005
#2005024
Î“cŒõˆę, ƒAƒeƒBƒbƒg ƒ^ƒ€ƒ^ƒJ[ƒ“, ũˆä‹MN, "1.8V CMOSƒvƒƒZƒX‚É‚æ‚鍂‘ψģƒIƒyƒAƒ“ƒv," “dŽqî•ņ’ʐMŠw‰ï@2005”N‘‡‘å‰ïu‰‰˜_•ķW, pp.13, Mar. 2005 (PDF)
#2005025
T. Sekitani, Y. Kato, S. Iba, T. Sakurai, and T. Someya, "High-Temperature Operation of Pentacene Field-Effect Transistors with Polyimide Gate Insulators," I1.9, Material Research Society Spring Meeting, Symposium I, "Organic Thin-Film Electronics, Mar. 2005
#2005026
Î“cŒõˆę, ũˆä‹MN, "Outside-Railo—Í‚ð‚ā‚‚‘ψģ‰‰ŽZ‘•Ší," “Œ‹ž‘åŠw 21Ē‹ICOE –Ē—ˆŽÐ‰ï‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJ@•―Ž16”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp..2-3, Mar. 2005
#2005027
ũˆä‹MN, "‚ ‚į‚ä‚éęŠ‚É‹@”\‚𖄂ߍž‚ށ@‹Č‚Š‚éƒfƒoƒCƒX," Nikkei BYTE, pp.56-64, Mar. 2005
#2005028
Danardono Dwi Antono, ũˆä‹MN, "On-chip Digital Oscilloscope for Signal Integrity Study," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆ‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž16”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp.10-11, Mar. 2005
#2005029
ėŒû”Ž, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ŠÖ’J‹B, õ’J—ē•v, ũˆä‹MN, "A Sheet-Type Scanner Based on a 3D-Stacked Organic-Transistor Circuit Using Double Word-Line and Bit-Line Structure," ISSCC2005 •ņ‰ï, Mar. 2005
#2005030
S. Iba, T. Sekitani, Y. Kato, T. Sakurai, and T. Someya, "Pentacene Field-effect Transistors with 230-nm-thick Polyimide Gate Dielectric Layers," Giant-Area Electronics on Nonconventional Substrrates, Apr. 1, 2005
#2005031
Atit Tamtrakarn and T. Sakurai, "Very low-power Analog/RF circuit design for ubiquitous electronics," •―Ž17”N“x@‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw21Ē‹ICOE–Ē—ˆƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†‹ģˆįƒZƒ“ƒ^[, pp.12-13, Apr. 21, 2005
#2005032
A. Tantrakarn, ũˆä‹MN, "Very low-power Analog/RF circuit design for ubiquitous electronics," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆŽÐ‰ï‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž16”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw21Ē‹ICOE–Ē—ˆƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†‹ģˆįƒZƒ“ƒ^[, pp.12-13, Apr. 21, 2005
#2005033
T. Sakurai, "How can we achieve Low-Power and High-Performance?," 2005 IEEE Internatiional Confernce on Integrated Circuit and Technology, pp.112, May 10, 2005
#2005034
Canh Quang Tran, H. Kawaguchi, and T, Sakurai, "Low-power High-speed Level Shifter Design for Block-level Dynamic Voltage Scaling Environment," IEEE International Conference on Integrated Circuit Design and Technology, Texas, USA, 1, pp.229-232, May 11, 2005 (PDF)
#2005035
T. Sakurai, "Perspectives of Low-Power Integrated Circuit Design for Ubiquitous Electronics," IT SoC International Symposium, Yonsei Uni., May 13, 2005
#2005036
õ’J—ē•v, ũˆä‹MN, ŠÖ’J‹B, ėŒû”Ž, "ƒiƒmˆóü‚Æ—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‹Zp," ‘æ‚R‰ņƒ|ƒŠƒ}[Œõ‰ņ˜HŒĪ‹†‰ï(POC)uƒiƒmƒCƒ“ƒvƒŠƒ“ƒg‚ÆŒõ‰ņ˜H‚Ö‚Ė‰ž—pv, iŠ”j–L“c’†‰›ŒĪ‹†Š, May 20, 2005
#2005037
Canh Quang Tran, H. Kawaguchi, and T, Sakurai, "More Than Two orders of Magnitude Leakage Current Reduction in Look-Up Table for FPGA's," IEEE International Symposium on Circuits and Systems, pp.4701-4704, May 2005 (PDF)
#2005038
K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Subthreshold-Leakage Suppressed Switched Capacitor Circuit Based on Super Cut-Off CMOS (SCCMOS)," IEEE International Symposium on Circuits and Systems, pp.3119-3122, May 2005
#2005039
T. Someya, T. Sekitani, H. Kawaguchi, S. Iba, and Y. Kato, "Recent Advances in Applications of Organic Inergrated Circuits for Large-Area Electronics," 2005 IEEE Internatiional Confernce on Integrated Circuit and Technology, pp.57-62, May 2005
#2005040
ŽO‰Y“T”V, aŒû‘å‰î, ˆäãáÁ—œ, ũˆä‹MN, •“c’‰L, "195Gb/s 1.2W “d—͐§Œä‹@”\•t‚Ŧ3ŽŸŒģÏ‘wŒ^—U“ąŒ‹‡–ģü’ī”zü," “dŽqî•ņ’ʐMŠw‰ï‹Z•ņ, 105, 96, pp.pp. 45-50, May 2005 (PDF)
#2005041
ũˆä‹MN, "‹Č‚Š‚éƒXƒLƒƒƒi[@—L‹@”ž“ą‘Ė‚ÅŠJ”­," “Œ‘å‚ÍŽå’Ģ‚·‚é@“Œ‹ž‘åŠwV•·ŽÐ, pp.168, May 2004
#2005042
ėŒû”Ž, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ŠÖ’J‹B, õ’J—ē•v, ũˆä‹MN, "“ņdƒ[ƒhü‚Æ“ņdƒrƒbƒgü‚ð—p‚Ē‚―3ŽŸŒģÏ‘wƒV[ƒgŒ^ƒXƒLƒƒƒi," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ‰ï, ICD2005-23, pp.19-21, May 2005
#2005043
õ’J—ē•v, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‚Æ‘å‹K–Í—L‹@ƒZƒ“ƒT‹Zp‚ĖŒŧó‚ƏŦ—ˆ“W–]," ”ž“ą‘Ė/FPD“Á•ĘƒZƒ~ƒi[u—L‹@ƒfƒoƒCƒX‚ĖŒŧó‚ƏŦ—ˆ“W–]v, ŠwŽm‰ïŠŲ, June 21, 2005
#2005044
K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T- Switch (AT-Switch) and Super Cut-off CMOS," IEEE/JSAP Symposium on VLSI Circuits Digest of Technical Papers, pp.122-125, June 2005 (PDF)
#2005045
Kyu-won Choi, Yingxue Xu, and T. Sakurai, "Optimal zigzag (OZ): an effective yet feasible power-gating scheme achieving two orders of magnitude lower standby leakage," IEEE Symposium on VLSI Circuits, pp.312-315, June 2005
#2005046
F.R. Saliba, H. Kawaguchi, and T. Sakurai, "Experimental verification of row-by-row variable VDD scheme reducing 95% active leakage power of SRAMs," IEEE Symposium on VLSI Circuits, pp.162-165, June 2005
#2005047
T. Someya, T. Sekitani, and T. Sakurai, "(Invited) Mechanical flexibility and high temperature operation of organic field-effect transistors," International Symposium on Molecular Conductors ---- Novel functions of molecular conductors under extreme conditions -Scientific Research on Priority Areas,Japan Shonan Village Center, —tŽR, July 17, 2005
#2005048
T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, S. Iba, Y. Kato, and Y. Noguchi, "(Invited) Organic transistor integrated circuits for large-area sensors: sheet image scanner and electronic skins," ORGANIC FIELD-EFFECT TRANSISTORS IV, Optics & Photonics, SPIE,, San Diego, California,, July 31, 2005
#2005049
(Invited) T. Someya and T. Sakurai, "Organic transistors for large-area sensor applications," Symposium "Chemistry in Electronics", the Eleventh Asian Chemical Congree (11thACC2005., Korea University, Seou, Aug. 24, 2005
#2005050
T. Someya, Y. Kato, T. Sekitani, S. Iba, Y. Noguchi, Y. Murase, H. Kawaguchi, and T. Sakurai, "Conformable, flexible, large-area networks of pressure and thermal sensors with organic transistor active matrixes," Proceedings of the National Academy of Sciences of the United States of America, , 102, Issue 35, pp.12321-12325, Aug. 30, 2005 (PDF)
#2005051
N. Miura, D. Mizoguchi, T. Sakurai, and T. Kuroda, "Analysis and Design of Inductive Coupling and Transceiver Circuit for Inductive Inter-Chip Wireless Superconnect," IEEE Journal of Solid-State Circuits (JSSC), 40, 4, pp.pp. 829-837, Aug. 2005 (PDF)
#2005052
ˆÉ’ëMŒá, ŠÖ’J‹B, ‰Á“Ą—Sė, ‚–ؐMˆę, ũˆä‹MN, õ’J—ē•v, "ƒ_ƒuƒ‹ƒQ[ƒg\‘Ē‚É‚æ‚é—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ė臒l“dˆģ§Œä," ‘æ66‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ï, “ŋ“‡‘åŠw, Sep. 9, 2005
#2005053
–ėŒû‹VW, ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ũˆä‹MN, õ’J—ē•v, "ƒ|ƒŠƒCƒ~ƒh‚ĖƒCƒ“ƒNƒWƒFƒbƒg“h•z‚Æ—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ö‚Ė‰ž—p," ‘æ66‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ï, “ŋ“‡‘åŠw, Sep. 9, 2005
#2005054
Atit Tamtrakarn, K. Ishida, and T. Sakurai, "A 20% Power Reduction in Two-stage Opamp by Source-Degenerated Active-Load Phase Compensation," Solid State Devices and Materials, Sep. 14, 2005
#2005055
Atit Tamtrakarn and T. Sakurai, "Wideband Low Noise Amplifier for 80-960MHz Ultra-wideband Transceiver," “dŽqî•ņ’ʐMŠw‰ï@ƒ\ƒTƒCƒeƒB‘å‰ï, Sep. 21, 2005
#2005056
–ėŒû‹VW, ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ”ä’ØaŽũ, ũˆä‹MN, õ’J—ē•v, "’ቷd‰ŧƒ|ƒŠƒCƒ~ƒh‚ðƒQ[ƒgâ‰–Œ‚Æ‚ĩ‚―—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^|DC “ÁŦ, ‘Ï”MŦ, ‹ü‹ČŽŽŒą, ˆóüv, ," 2Q08, ƒVƒ“ƒ|ƒWƒEƒ€u—L‹@ƒGƒŒƒNƒgƒƒjƒNƒXÞ—ŋ‚Ė‡ŽE“dŽqEŒõ‹@”\v, ‘æ54‰ņ‚•ŠŽq“Ē˜_‰ï, , ŽRŒ`‘åŠw@Ž”’ėƒLƒƒƒ“ƒpƒX, Sep. 21, 2005
#2005057
’†‘šˆĀŒĐ, ũˆä‹MN, "‚ˆģ“dŒđ‚ðŽg—p‚ĩ‚―“dŒđƒmƒCƒY‚Ė’áŒļ," “dŽqî•ņ’ʐMŠw‰ï ƒ\ƒTƒCƒGƒeƒB‘å‰ï, C-12-19, Sep. 22, 2005
#2005058
T. Sakurai, "Advances and Pespectives on Low-power Integrated Circuits for Ubiquitous Electronics," The 21st Century COE in Electrical Engineering and electronics for the Active and Creative World, “Œ‹ž‘åŠw, pp.93-98, Oct. 11, 2005
#2005059
(Invited) T. Someya, T, Sakurai, T. Sekitani, H. Kawaguchi, Y, Kato, and S. Iba, "Pocket Scanner using Organic Transistors and Detectors," IEEE Lasers and Electro-Optics Society, Sydney, Australia, Oct. 23, 2005
#2005060
T. Sakurai, "Moore's Law plus-What will be needed in interconnects, othe than scaling, from an applications perspective?," Twenty second International VLSI multilevel interconnection conference, “Œ‹ž‘åŠw, pp.19, Oct. 30, 2005
#2005061
T. Someya, T. Sekitani, Shi. Iba, Y. Kato, Y. Noguchi, K. Hizu, and T. Sakurai, "(Invited) Conformable electronic artificial skins with organic transistor integrated circuits," Korea-Japan Joint Forum(KJF) 2005 on Organic Materials for Electronics, Daejeon, Korea, Oct. 26-29, 2005
#2005062
K. Onizuka and T. Sakurai, "VDD-Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time," IEEE Asian Solid-State Circuits Conference, Hsinchu, Taiwan, Session6-1, pp.145-148, Nov. 2, 2005 (PDF)
#2005063
Canh Quang Tran, H. Kawaguchi, and T, Sakurai, "95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping," IEEE Asian Solid-State Circuits Conference, Hsinchu, Taiwan, 6, pp.149-152, Nov. 2, 2005 (PDF)
#2005064
ũˆä‹MN, •“c’‰L, "”ž“ą‘ĖWÏ‰ņ˜H‘•’u," ‘æ2‰ņ@P&Iƒpƒeƒ“ƒgƒRƒ“ƒeƒXƒg@ƒpƒeƒ“ƒgEƒIƒuĨƒUEƒCƒ„[, ˆęƒc‹īƒƒ‚ƒŠƒAƒ‹ƒz[ƒ‹, Nov. 8, 2005
#2005065
S. Iba, Y. Kato, T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Use of laser drilling in the manufacture of organic inverter circuits," Analytical and Bioanalytical Chemistry, 384, pp.374 - 377, Nov. 11, 2005
#2005066
Kyu-won Choi, Y. Xu, K. Inagaki, and T. Sakurai, "Optimal zigzag scheme achieving lower standby leakage," International Symposium on Quantum Dots and Nanoelectronics, Tokyo Garden Place, Nov. 18, 2005
#2005067
ũˆä‹MN, "’áÁ”ï“d—͐݌v‚ĖÅ‹ß‚Ė“ŪŒü," Low-PowerƒfƒUƒCƒ“ƒZƒ~ƒi[2005, ”Ņ“c‹ī, Nov. 28, 2005
#2005068
T. Someya, Y. Kato, S. Iba, Y. Noguchi, T. Sekitani, H. Kawaguchi, and T. Sakurai , "Integration of organic FETs With Organic Photodiodes for a Large Area, Flwxible, and Lightweight Sheet Image Scanners," IEEE Transactions on Electron Devices, 52, 11, pp.2502-2511, Nov. 2005 (PDF)
#2005069
K. Ishida, A. Tamtrakarn, H. Ishikuro, and T. Sakurai, "An Outside-Rail Opamp Design Targeting for Future Scaled Transistors," 2005 IEEE Asian Solid-State Circuits Conference, pp.73-76, Nov. 2005
#2005070
T. Someya, T. Sakurai, and T. Sekitani, "(Invited) Flexible, Large-Area Sensors and Actuators with Organic Transistor Integrated Circuits," IEEE International Electron Devices Meeting, Washington, DC, Dec. 5, 2005
#2005071
Y. Kato, S. Iba, T.Sekitani, Y. Noguchi, K. Hizu, X. Wang, K. Takenoshita, Y. Takamatsu, S. Nakano, K. Fukuda, K. Nakamura, T. Yamaue, M. Doi, K.. Asaka, H. Kawaguchi, M. Takamiya, T. Sakurai, and T. Someya, "A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor active matrix," IEEE International Electron Devices Meeting, Washington, DC, Dec. 5, 2005
#2005072
T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, Y. Kato, and S. Iba, "(Invited) A Sheet Image Scanner with Organic Transistor Integrated Circuits," 2005 International Display Workshops (IDW/ADf05), ‚ž, Dec. 6, 2005
#2005073
Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, and Takayasu Sakurai, "Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's," IEICE Transactions on Electronics, E88-C, 4, pp.760-767, 2005
#2005074
T. Sekitani, S. Iba, Y. Kato, Y. Noguchi, T. Someya, and T. Sakura, "Ultra-flexible organic field-effect transistors embedded at a neutral strain position," Applied Physics Letters 87, pp.173502, 2005 (PDF)
#2005075
T. Sekitani, S. Iba, T. Sekitani, Y. Kato, T. Someya, and T. Sakurai, "Suppression of DC bias stress-induced degradation of organic field-effect transistors using postannealing effects ," Applied Physics Letters 87, pp.073505 , 2005 (PDF)
#2005076
S. Iba, T. Sekitani, Y. Kato, T. Someya, H. Kawaguchi, M. Takamiya, T. Sakurai, and S. Takagi, "Control of threshold voltage of organic field-effect transistors with double-gate structures," Applied Physics Letters 87, pp.023509 ., 2005 (PDF)
#2005077
T. Sekitani, Y. Kato, S. Iba, and T. Someya, "Bending Effect of Organic Field-Effect Trasistors with Polyimide Gate Dielectric Layers," Japanese Journal of Applied Physics, 44, pp.2841-2844, 2005 (PDF)
#2005078
•“c’‰L, "Leakage in Nanometer CMOS Technologies (Chapter 4: Body Biasing),," Springer Science+Business Media, Inc., ISBN 0-3872-5737-3, 2005
#2005079
Y. Noguchi, T. Sekitani, Y. Kato, S. Iba, T. Sakurai, and T. Someya, "Inkjet Printing of Polyimide Precursors and Its Application to Organic Field-Effect Transistors," 2005 MRS Fall Meeting, Hynes Convention Center and Sheraton Boston Hotel, Boston, 2005., Massachusetts, 2005
#2005080
T. Sekitani, S. Iba, Y. Kato, Y. Noguchi, T. Sakurai, and T. Someya, "Organic Field-Effect Transistors with Suppressed DC Bias-Stress Degradations," 2005 MRS Fall Meeting, Hynes Convention Center and Sheraton Boston Hotel, Boston, 2006., Massachusetts, 2005
#2005081
T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, S. Iba, and Y. Kato, "(Invited) Recent Advances in Applications of Organic Integrated Circuits for Large-Area Electronics," International Conference on IC Design and Technology, Austin, TX, 2005
#2005082
ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ũˆä‹MN, õ’J—ē•v, "ƒtƒŒƒLƒVƒuƒ‹—L‹@ƒgƒ‰ƒ“ƒWƒ^‚Ė“d‹C“`“ą“ÁŦ‚É‚Ļ‚Ŋ‚éˆģkEL’Ģ˜c‚Ý‚ĖŒø‰Ę," Þ—ŋƒfƒoƒCƒXƒTƒ}[ƒ~[ƒeƒBƒ“ƒO, —L‹@ƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†‰ï, ‹@ŠBU‹ŧ‰ïŠŲ, 2005
#2005083
õ’J—ē•v, ũˆä‹MN, ėŒû”Ž, ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, –ėŒû‹VW, ‘šĢ—m‰î, "u—L‹@Þ—ŋĖ—p‚Å‹Č‚°‚į‚ę‚éƒXƒLƒƒƒi[F‰ņ˜H‹Zp‚ÅŽs”Ė•Ā‚ݍ‚Ŧ”\‚ðŽĀŒŧ," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 2ŒŽ28“ú†, pp.123-132, 2005
#2005084
T. Sekitani, S. Iba, Y, Kato, Y. Noguchi, T, Sakurai, and T. Someya, "SUBMILLIMETER RADIUS BENDABLE ORGANIC FIELD-EFFECT TRANSISTORS," The 21st International Conference on Amorphous and Nanocrystalline Semiconductors (ICANS 21), Calouste Gulbenkian Foundation,, Portugal, Lisbon, 2005
#2005085
ũˆä‹MN,"ƒV[ƒgóƒXƒLƒƒƒi‚͐ĒŠE‚ð‚Į‚Ī•Ï‚Ķ‚é‚Ė‚ЁHgüh‚Å‚Í‚Č‚­g–ʁh‚ÅŠÏ‚éƒXƒLƒƒƒiI,"ŒŽŠ§ƒAƒXƒL[, 2ŒŽ†, No.332, 2005
#2005086
ũˆä‹MN,"ƒV[ƒgŒ^ƒXƒLƒƒƒi‚ĖŠJ”­@—L‹@”ž“ą‘Ė‚ŃXƒLƒƒƒi‚ðŠJ”­@ƒXƒLƒƒƒi‚Ėƒ‚ƒoƒCƒ‹‰ŧ‚āŽĀŒŧ,"@Electronic Journal, p.76, 1ŒŽ†, 2005
#2005087
ũˆä‹MN,"ƒ\ƒtƒg‚ƃn[ƒh‚Ė˜AŒg‚ð‹­‰ŧ@‰ņ˜HÝŒv‚ĖŽĐ—R“x‚ðŒüã," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX, pp.80-81, Aug. 2005
#2005088
ũˆä‹MN,"ƒŠ[ƒN“d—Ž‚Í‚ą‚Ī—}‚Ķ‚éi6jŠî”ƒoƒCƒAƒX“dˆģ‚ð—p‚Ē‚―‰Â•Ï‚ĩ‚Ŧ‚Ē’l“dˆģ§Œä‚Å’áŒļ,h“úŒoƒGƒŒƒNƒgƒƒjƒNƒX2005”N4ŒŽ11“ú†, pp.120-126, 2005
#2005089
ũˆä‹MN,"i“Á•Ęu‰‰)ƒ†ƒrƒLƒ^ƒXEƒGƒŒƒNƒgƒƒjƒNƒX‚ÉŒü‚Ŋ‚―’áÁ”ï“d—͐݌v‹Zp‚Æ—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‰ņ˜H," ”ž“ą‘Ė‹Zpƒ[ƒhƒ}ƒbƒvę–åˆÏˆõ‰ï‘æˆę•”wITRS 2004 Update‚ÉŒĐ‚éĄŒã‚ĖLSI‹Zp‚Ė•ûŒüŦx, pp.3C-1-3C-21, Mar.3, 2005

2004

#2004001
T. Someya and T. Sakurai, "Electronic skin senses touch," Science News, 165, pp.45, Jan. 17, 2004

#2004002
T. Miyazaki and T, Sakurai, "Research on Low-Power VLSI Circuit Design for Ubiquitous Electronics," CŽm˜_•ķ, “Œ‹ž‘åŠw, Feb. 9, 2004

#2004003
T. Sakurai, "Adaptive Circuit Techniques for Managing Variations," IEEE International Solid-State Circuits Conference Digest of Technical Papers, U.S.A., Feb. 19, 2004 (PDF)

#2004004
õ’J—ē•v, ũˆä‹MN, "•\Ž†u”į•†ŠīŠo‚ðŽ‚Â“™g‘働ƒ{ƒbƒgv," NEW MEDIA, ‘nŠ§20”N+2†, pp.•\Ž†, Feb. 2004

#2004005
ũˆä‹MN, "ƒIƒsƒjƒIƒ“ƒŠ[ƒ_[‚ĖŽ˜_‚ð’m‚é," ŒŽŠ§PC|Webmagazine, 144, pp.84, Feb. 2004

#2004006
ũˆä‹MN, "2010”N—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^@VƒAƒvƒŠ‚ŠŒŧŽĀ‚É," Nikkei MICRODEVICES, 224, 2, pp.46-47, Feb. 2004

#2004007
õ’J—ē•v,@ũˆä‹MN, "‚­‚É‚á‚­‚É‚á‹Č‚Š‚郍ƒ{ƒbƒg—p‚Ė”į•†," ƒlƒCƒ`ƒƒ[ƒCƒ“ƒ^[ƒtƒF[ƒX, 19, pp.91, Feb. 2004

#2004008
T. Someya, H. Kawaguchi, and T. Sakurai, "Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin," IEEE International Solid-State Circuits Conference Digest of Technical Papers, U.S.A., Feb. 2004 (PDF)

#2004009
D. Mizoguchi, Y. Yusof, N. Miura, T. Sakurai, T. Kuroda, "A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling," IEEE International Symposium on Quality Electronic Design, U.S.A., Session7-6, Feb. 2004 (PDF)

#2004010
T. Sakurai, "Perspectives in Power-Aware and Large-Area Integrated Circuits for Ubiquitous Electronics," International Symposium on Electronics for Future Generations, Tokyo, pp.71-74, Mar. 10, 2004 (PDF)

#2004011
T. Someya and T. Sakurai, "Flexible, Large-Area sensor Matrix with Organic Taransistor-Based Circuits," 3rd International Symposium on Organic Molecular Electronics (ISOME2004) , Kyoto, Mar. 18, 2004 (PDF)

#2004012
Î“cŒõˆę, ũˆä‹MN, "•‰ƒoƒCƒAƒX§ŒäƒXƒCƒbƒ`‚ð—p‚Ē‚―‚ļ“xƒXƒCƒbƒ`ƒLƒƒƒpƒVƒ^‰ņ˜H," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆ‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž15”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp.2-3, Mar. 2004 (PDF)

#2004013
ƒ`ƒƒƒ“EƒNƒƒ“EƒJƒCƒ“, ũˆä‹MN, "FPGA‚Ė’áÁ”ï“d—͉ŧ‚ÉŠÖ‚·‚éŒĪ‹†," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆ‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž15”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp.4-5, Mar. 2004 (PDF)

#2004014
Danardono Dwi Antono, ũˆä‹MN, "Signal Integrity in Deep Submicron VLSI Interconnects," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆ‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž15”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp.6-7, Mar. 2004 (PDF)

#2004015
Atit Tamtrakarn, ũˆä‹MN, "Low-power short-range wireless RF transceiver systems for sensor network applications," “Œ‹ž‘åŠw21Ē‹ICOEu–Ē—ˆ‚ð’S‚ĪƒGƒŒƒNƒgƒƒjƒNƒX‚Ė“WŠJv•―Ž15”N“x‘åŠw‰@”ŽŽm‰Û’öŠwķ•ņ‘, “Œ‹ž‘åŠw, pp.8-9, Mar. 2004 (PDF)

#2004016
T. Someya, H.Kawaguchi, and T.Sakurai, "Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin," ISSCC2004•ņ‰ï, “Œ‹ž‘åŠw, Mar. 17, 2004

#2004017
T. Sakurai, "Perspective of Power-Aware Electronics," IEEE Distinguished Lecturer Program in Taiwan, Taiwan, Mar. 2004

#2004018
ũˆä‹MN, "•”•i‚ĖŒÂŦ‚ðķ‚Đ‚ĩŦ”\Œüã, •ā—Ŋ‚Ü‚č‰ü‘P," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 870, pp.120-129, Mar. 29, 2004

#2004019
ˆÉ’ëMŒá, ‰Á“Ą—Sė, ŠÖ’J‹B, ėŒû”Ž, ũˆä‹MN, õ’J—ē•v, "ƒŒ[ƒU[ƒhƒŠƒ‹‰ÁH‚ð—p‚Ē‚―—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ĖƒCƒ“ƒo[ƒ^‰ņ˜H," t‹G‘æ51‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰ , “Œ‹žH‰Č‘åŠw, 28p-ZN-3, Mar. 2004

#2004020
ŠÖ’J‹B, ˆÉ’ëMŒá, ‰Á“Ą—Sė, ėŒû”Ž, ũˆä‹MN, õ’J—ē•v, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ĖV‚ĩ‚Ē‰ž—p‚ð‘ņ‚­ƒtƒŒƒLƒVƒuƒ‹‘å–ĘÏƒZƒ“ƒT[," t‹G‘æ51‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰ , “Œ‹žH‰Č‘åŠw, 28p-ZN-14, Mar. 2004

#2004021
‰Á“Ą—Sė, ˆÉ’ëMŒá, Ž›–{—š•―, ŠÖ’J‹B, ėŒû”Ž, ũˆä‹MN, õ’J—ē•v, "’ቷd‰ŧƒ|ƒŠƒCƒ~ƒh‚ðƒQ[ƒgâ‰–Œ‚É—p‚Ē‚―ƒyƒ“ƒ^ƒZƒ““dŠEŒø‰Ęƒgƒ‰ƒ“ƒWƒXƒ^," , “Œ‹žH‰Č‘åŠw, 28p-ZN-15, Mar. 2004

#2004022
ũˆä‹MN, "LSIƒVƒXƒeƒ€‚Ė‰Û‘č‚ƐV‚ĩ‚ĒƒAƒvƒŠƒP[ƒVƒ‡ƒ“," ‰ï, pp.23-51, Apr. 7, 2004

#2004023
ũˆä‹MN, "‚ĩ‚Ŧ‚Ē’l“dˆģ‚Ė’áŒļ‚ŠŒĀŠE@‰ņ˜H‹Zp‚Š“đ‚ðŠJ‚­," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 872, pp.110-127, Apr. 26, 2004

#2004024
õ’J—ē•v, ũˆä‹MN, ėŒû”Ž, ŠÖ’J‹B, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ĖV‚ĩ‚Ē‰ž—p‚ð‘ņ‚­ƒtƒŒƒLƒVƒuƒ‹‘å–ĘÏƒZƒ“ƒT," ‰ž—p•Ļ—, ‘æ73ŠŠ, ‘æ5†, 2004

#2004025
T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Organic field-effect transistors with bending radius down to 1 mm," 2004 Materials Research Society (MRS) Spring Meeting, USA(SF), Apr. 2004 (PDF)

#2004026
H. Kawaguchi, T. Someya, T. Sekitani, and T. Sakurai, "Cut-and-Paste Customization of Organic FET Integrated Circuit and Its Application to Electronic Artificial Skin," IEEE Journal of Solid State Circuits, Vol., No., Apr. 2004 (PDF)

#2004027
T. Sakurai, "Perspectives of Low-Power VLSI's," IEICE Transactions on Electronics, E87-C, 4, pp.429-437, Apr. 2004 (PDF)

#2004028
Y. Kato, S. Iba, R. Teramoto, T. Sekitani, and T. Someya, "High mobility of pentacene field-effect transistors with polyimide gate dielectric layers," Applied Physics Letters, May 10, 2004

#2004029
T.Sakurai, "Perspectives of Low Power Electronics ," 2004 Internasional Confernce on Integrated Circuit Design and Technology, Austin, Texas, pp.1-147, May 17, 2004

#2004030
S.Iba, Y.Kato, T.Sekitani, T.Someya, H.Kawaguchi, and T.Sakurai, "Organic inverter circuits with via holes formed by CO2 laser drill machine," Applied Physics Letters, May 2004

#2004031
ũˆä‹MN, "ƒ[ƒpƒ[LSI‹Zp‚ƃ[ƒpƒ[‚Š‘ņ‚­ĒŠE," SEMI FORUM JAPAN 2004, ‘åã, pp.1-21, June 17, 2004

#2004032
ũˆä‹MN, "uƒX[ƒp[ƒRƒlƒNƒgv‚Ė‘_‚ĒAŒŧóAŦ—ˆ“W–]‚ɂ‚Ē‚Ä," Q&A ƒGƒŒƒNƒgƒƒjƒNƒX‚ƍ‚•ŠŽq, pp.40-41, June 2004 (PDF)

#2004033
õ’J—ē•v,@ŠÖŒû‹B, ėŒû”Ž, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ė‘å–ĘÏƒZƒ“ƒT[‰ž—p," ŒÅ‘Ė•Ļ—, 39, 460, pp.77-83, June 2004 (PDF)

#2004034
ũˆä‹MN, "ƒVƒXƒeƒ€EƒCƒ“EƒpƒbƒP[ƒW‚ƃX[ƒp[ƒRƒlƒNƒg‚Ö‚ĖŠú‘Ō," ŽĀ‘•‹ZpƒKƒCƒhƒuƒbƒN2004iH‹Æ’ēļ‰ïj, 7ŒŽ†, •Ęû, pp.2, July 2004

#2004035
T. Kuroda and T. Sakurai, "Overview of Low-Power ULSI Circuit Techniques," HIGH-PERFORMANCE SYSTEM DESIGN, pp.198-207, 2004

#2004036
\ŽR@Œ\‰î, ŽOâ@’q, ‘Šâ@ˆę•v, Ý’ˁ@r”V, “āŽR@–M’j, Î‹ī@Fˆę˜Y, ėŒû@”Ž, ũˆä@‹MN, "CPUÁ”ï“d—͍íŒļ‚Ė‚―‚ß‚ĖŽü”g”-“dˆģ‹Ķ’ēŒ^“d—͐§Œä•ûŽŪ‚ĖÝŒvƒ‹[ƒ‹‚ƃtƒB[ƒhƒoƒbƒN—\‘Š•ûŽŪ‚É‚æ‚é“K—p," “dŽqî•ņ’ʐMŠw‰ï˜_•ķŽ, J87-D-I , 4, pp.452-461, Apr. 2004

#2004037
H. Kawaguchi, Y. Shin, and T. Sakurai, "ƒĘITRON-LP: Power-Conscious Real-Time OS Based on Cooperative Voltage Scaling for Multimedia Applications," IEEE Transaction on Multimedia, Vol., No., 2004 (PDF)

#2004038
T. Someya, T. Sekitani, S. Iba, Y. Kato, H. Kawaguchi, and T. Sakurai, "A Large-Area, Flexible Pressure Sensor Matrix with Organic Field-Effect Transistors for Artificial Skin Applications," , 2004 (PDF)

#2004039
T. Sakurai and T. Someya, "Expectations for Organic Transistor IC's and Large-Area Electronics," EXTENDED ABSTRACTS OF THE 23red ELECTRONIC MATERIALS SYMPOSIUM, ˆÉ“Ī’·‰Š, K2, pp.297-300, July 7, 2004

#2004040
K. Kanda, S. Hattori, and T. Sakurai, "90% write power-saving SRAM using sense-amplifying memory cell," IEEE J. Solid-State Circuits, Vol.39, No.6, pp.927-933, Jan. 2004 (PDF)

#2004041
ũˆä‹MN, "Šî’ēu‰‰@”ũŨ‰ŧ‚ÅŒĐ‚Ķ‚Ä‚Ŧ‚―LSIÝŒv‚Ė‹Zp“I‰Û‘č," ‘æ13‰ņ”ž“ą‘ĖƒvƒƒZƒXƒVƒ“ƒ|ƒWƒEƒ€, pp.8-33, Sep. 16, 2004

#2004042
Fayez R. Saliba, and T. Sakurai, "Low-Voltage Low-Power SRAM and Flip-Flop Design for Deep-Submicron VLSI's," CŽm˜_•ķ, “Œ‹ž‘åŠw, Aug. 23, 2004

#2004043
T. Sakurai, "Low Power Digital Circuit Design," European Solid-State Circuits Conference, Leuven, Belgium, Sep. 21-23, 2004 (PDF)

#2004044
õ’J—ē•vAũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‚Æ‘å–ĘÏƒGƒŒƒNƒgƒƒjƒNƒX," ‘æ65‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ïƒVƒ“ƒ|ƒWƒEƒ€ u—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^|| ŽĀ—p‰ŧ‚ÍŒĐ‚Ķ‚Ä‚Ŧ‚―‚Đ, “Œ–k‘åŠw, Sep. 2004 (PDF)

#2004045
T.Someya, T.Sakurai, T.Sekitani, H.Kawaguchi, S.Iba, and Y.Kato, "Organic transistor ICs for large-area sensors," Korea Japan Joint Forum 2004 , Okinawa, Nov. 3, 2004 (PDF)

#2004046
õ’J—ē•vCũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ð—p‚Ē‚―‘å–ĘÏƒZƒ“ƒT[WÏ‰ņ˜H‹Zp," ‰ž—p•Ļ—Šw‰ïŠÖžŽx•”ƒVƒ“ƒ|ƒWƒEƒ€ , ‘åã, Nov. 26, 2004

#2004047
ũˆä‹MN, "ŽYŠw˜AŒg‚𐎌ũ‚ģ‚đ‚é‚ā‚Īˆę‚‚Ė•û–@," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX/“úŒoƒ}ƒCƒNƒƒfƒoƒCƒX/“úŒo‚ā‚Ė‚­‚č‡“ŊŠé‰æ, ŠwķŒü‚Ŋ“Á•Ę•ŌW”Å, pp.41-42, 2004 (PDF)

#2004048
õ’J—ē•v, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‚Æ‘å–ĘÏƒGƒŒƒNƒgƒƒjƒNƒX," H‹Æ’ēļ‰ï@‘Û‹Zpî•ņŽ, 12ŒŽ†, pp.172-178, Dec. 2004

#2004049
Canh Q. Tran, Takayasu Sakurai, "’á“dˆģ‘Ήž‚ĖƒŒƒxƒ‹ƒRƒ“ƒo[ƒ^," “dŽqî•ņ’ʐMŠw‰ï2004”N‘‡‘å‰ï, “Œ‹žH‹Æ‘åŠw, A-1-8, pp.8, Mar. 22, 2004 (PDF)

#2004050
‹{č—ēs, ƒ_ƒiƒ‹ƒhƒm@ƒhƒDƒC@ƒAƒ“ƒgƒm, Î“cŒõˆę, ũˆä‹MN, "•W€CMOSƒvƒƒZƒX‚ð—p‚Ē‚―‰đ”g”­ķƒfƒoƒCƒX," 2004”N“dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, “Œ‹ž, A-1, pp.17, Mar. 22, 2004

#2004051
õ’J@—ē•vCėŒû@”ŽCũˆä@‹MN, "Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, May 2004

#2004052
Atit Tamtrakarn, Takayasu Sakurai, "Medium-loss considerations for designing an ultra-wideband transceiver," “dŽqî•ņ’ʐMŠw‰ï2004”Nƒ\ƒTƒGƒeƒB‘å‰ï, ISSN 1349-144X, A-1, pp.17, Sep. 8, 2004 (PDF)

#2004053
“ŋ‰i˜aG@ũˆä‹MN, "Dual-VTH, dual-VDD, dual-W‚ðŽg‚Á‚―’áÁ”ï“d—̓‰ƒCƒuƒ‰ƒŠ‚ÉŠÖ‚·‚élŽ@," STARCƒVƒ“ƒ|ƒWƒEƒ€2004, V‰Ą•l‘Ûƒzƒeƒ‹, Sep. 9,

#2004054
ũˆä‹MN, "ƒŠ[ƒN“d—Ž‚Í‚ą‚Ī—}‚Ķ‚éi1j“d—Ž’l‚Ė2ƒPƒ^íŒļ‚Š‹}–ą@‰ņ˜H‹Zp‚Ė‘“Š“ü‚ÅŽĀŒŧ," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 9-13†, pp.154-161, Sep. 13, 2004

#2004055
‹S’ˍ_•― ũˆä‹MN, "ƒCƒ“ƒ_ƒNƒeƒBƒuƒJƒbƒvƒŠƒ“ƒO‚É‚æ‚é“d—Í“`‘—‰ņ˜HÅ“K‰ŧ‚ÉŠÖ‚·‚éˆęlŽ@," “dŽqî•ņ’ʐMŠw‰ï 2004”N Šî‘bE‹ŦŠEƒ\ƒTƒCƒGƒeƒB‘å‰ï, “ŋ“‡, A-1-3, pp.3, Sep. 21, 2004 (PDF)

#2004056
Î“cŒõˆę, ũˆä‹MN, "’á‚ĩ‚Ŧ‚Ē’lƒfƒoƒCƒX‚ð—p‚Ē‚―’á“dˆģ‹ė“ŪƒAƒiƒƒO‰ņ˜H," 2004”N“dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒGƒeƒB‘å‰ï, “ŋ“‡, A-1, pp.11, Sep. 21, 2004

#2004057
Kwu-Won Choi, Yingxue Xu, Takayasu Sakurai, "Power-Gating Switch Revisited: A Fine-Grain Optimization for Leakage-Aware CMOS Circuits," 2004”N“dŽqî•ņ’ʐMŠw‰ïŠî‘bE‹ŦŠEƒ\ƒTƒCƒGƒeƒB‘å‰ï, “ŋ“‡‘åŠw, A-3-6, pp.pp.61, Sep. 23, 2004 (PDF)

#2004058
ũˆä‹MN, "ƒŠ[ƒN“d—Ž‚Í‚ą‚Ī—}‚Ķ‚éi2jŽĀŒŧ‰ŧi‚Þƒfƒ…ƒAƒ‹Vth‚âƒTƒCƒWƒ“ƒOƒfƒ…ƒAƒ‹Vdd‚Ė‰Û‘č‚̓RƒXƒg," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 9-27†, pp.136-143, Sep. 27, 2004

#2004059
Jin-Hyeok Choi, Yingxue Xu, Takayasu Sakurai, "Statistical Leakage Current Reduction in High-Leakage Environments Using Locality of Block Activation in Time Domain," IEEE Journal of Solid-State Circuits, Vol.Vol.37, No.No.9, pp.pp.1497-1503, Sep. 2004 (PDF)

#2004060
“ŋ‰i@˜aGCėŒû@”ŽCũˆä@‹MN, "VLSIÝŒv‚É‚Ļ‚Ŋ‚éDual VDD‰ņ˜H‚Ė“d—͍íŒļŒø‰Ę," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, Sep. 2004

#2004061
ũˆä‹MN, "ƒŠ[ƒN“d—Ž‚Í‚ą‚Ī—}‚Ķ‚éi3j‘Ō‹@Žž‚ĖƒŠ[ƒN“d—Ž‚̓pƒ[EƒQ[ƒeƒBƒ“ƒO‚ÅŒļ‚į‚·," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 10-11†, pp.138-144, Oct. 11, 2004

#2004062
ũˆä‹MN, "ƒŠ[ƒN“d—Ž‚Í‚ą‚Ī—}‚Ķ‚éi4j+0.7V‚Ė’á“dˆģ‚ɑΉž‰Â”\‚ȐVŒ^ƒpƒ[EƒQ[ƒeƒBƒ“ƒO‹Zp‚Š“oę," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 10-25†, pp.156-163, Oct. 25, 2004

#2004063
T. Miyazaki, T. Q. Canh, H. Kawaguchi, and T. Sakurai, "Observation of one-fifth-a-clock wake-up time of power-gated circuit," Proceedings of IEEE Custom Integrated Circuits Conference, pp.pp. 87-90, Oct. 2004 (PDF)

#2004064
õ’J@—ē•vCũˆä@‹MNCŠÖ’J@‹BCˆÉ’ë@MŒáC‰Á“Ą@—SėCėŒû@”Ž, "ƒ†ƒrƒLƒ^ƒXŽž‘ã‚ÉŠú‘Ō‚ģ‚ę‚é—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‹Zp‚ƃtƒHƒgƒ“," ‹ž“sƒiƒmƒeƒNƒNƒ‰ƒXƒ^[ƒtƒHƒgƒjƒbƒNƒZƒ~ƒi[, Dec. 2004

#2004065
T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, S. Iba, and Y. Kato," , , . 2004., "A Large-Area, Flexible, and Lightweight Sheet Image Scanner," IEEE International Electron Devices Meeting Digest of Technical Papers, #15.1, Dec. 2004

#2004066
T. Sakurai, "Perspectives of Low Power Electronics," 2004 IEEE International Confernce on Semiconductor Electronics, Kuala Lumpur, ‡VB(Parameswara ‡U, level2), Dec. 2004

#2004067
õ’J—ē•vCũˆä‹MNCėŒû”ŽCŠÖ’J‹B, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ĖV‚ĩ‚Ē‰ž—p‚ð‘ņ‚­ƒtƒŒƒLƒVƒuƒ‹‘å–ĘÏƒZƒ“ƒT[," ‰ž—p•Ļ—, 73i5j, pp.610-614, Mar. 2004 (PDF)
#2004068
õ’J—ē•vCũˆä‹MN,"—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^WÏ‰ņ˜H‹Zp‚Æ‘å–ĘÏƒGƒŒƒNƒgƒƒjƒNƒX, " u‚l•‚dv12ŒŽ†, pp.172-178, 2004
#2004069
ũˆä‹MN,"‹Č‚Š‚éƒtƒBƒ‹ƒ€óƒXƒLƒƒƒi‚ðŽŽė@ŒõŠwŒn‚â‹@ŠB•”•i‚Š•s—v‚É," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX2005”NVt†, p.5, 2004

2003

#2003001
ũˆä‹MN, "Åæ’[ƒVƒXƒeƒ€LSI‚ĖŒŧó‚Ɖۑč," “dŽqEî•ņ‹Zpƒ[ƒNƒVƒ‡ƒbƒv, pp.38-55, Jan. 14, 2003

#2003002
ũˆä‹MN, "–{‰đ‚ÅŒę‚鍡Œã‚Ė”ž“ą‘Ė‹Zpí—Š," ƒTƒCƒGƒ“ƒXƒtƒH[ƒ‰ƒ€, ŒãŠy‰€‰ïŠŲ, pp.‡V.1.1|‡V1.6, Jan. 16, 2003

#2003003
H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, and T. Sakurai, "A 0.5-V, 400-MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.106-107, Feb. 2003 (PDF)

#2003004
K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.186-187, Feb. 2003 (PDF)

#2003005
K. Min, H. Kawaguchi, T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.400-401, Feb. 2003 (PDF)

#2003006
Danardono Dwi Antono, Takayasu Sakurai, "Power Consumption Distribution in DSM Interconnects with Inductive Effects," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, “Œ–k‘åŠw, A-3-15, pp.82, Mar. 20, 2003 (PDF)

#2003007
ėŒû@”Ž, _“c@_ˆę, –ėĢ@_ˆę, •ž•”@’叚, ƒ_ƒiƒ‹ƒhƒm@ƒhƒDƒC@ƒAƒ“ƒgƒm, ŽR“c@‘å—T, ‹{č@—ēs, ˆîŠ_@ŒŦˆę, •―–{@r˜Y, ũˆä@‹MN, "A 0.5-V, 400-MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology," ISSCC2003•ņ‰ï, Mar. 2003

#2003008
ũˆä‹MN, "‰ņ˜HÝŒv‹Zp‚ĖÅV“ŪŒü," ƒVƒXƒeƒ€LSI‹Zp‚ÉŠÖ‚·‚é’ēļ•ņ‘, pp.66-82, Mar. 2003

#2003009
T. Sakurai, "Opportunities of Japanese Semiconductor Industry," ING Technical Seminar, Japan, pp.34, Apr. 22, 2003

#2003010
S. Misaka, K. Toyama, T. Aritsuka, K. Uchiyama, K. Aisaka, H. Kawaguchi, and T. Sakurai, "Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications," International Symposium on Low-Power and High-Speed Chips (COOL Chips), Apr. 2003

#2003011
_“c@_ˆę, ƒ_ƒiƒ‹ƒhƒm@ƒhƒDƒC@ƒAƒ“ƒgƒm, Î“c@Œõˆę, ėŒû@”Ž, •“c@’‰L, ũˆä@‹MN, "1.27Gb/s/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, ICD2003-16, pp.19-22, May 2003 (PDF)

#2003012
ėŒû@”Ž, _“c@_ˆę, –ėĢ@_ˆę, •ž•”@’叚, ƒ_ƒiƒ‹ƒhƒm@ƒhƒDƒC@ƒAƒ“ƒgƒm, ŽR“c@‘å—T, ‹{č@—ēs, ˆîŠ_@ŒŦˆę, •―–{@r˜Y, ũˆä@‹MN, "A 0.5V, 400MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, ICD2003-35, pp.55-58, May 2003 (PDF)

#2003013
T. Sakurai, "Low Power Circuits and Techniques," IEEE Custom Integrated Circuits Conference, USA(San Jose), 28, May 2003

#2003014
ũˆä‹MN, "LSI‚ĖV‹Ŧ’n‚ð‘ņ‚­ƒX[ƒp[ƒRƒlƒNƒg," ‰ŧŠwH‹ÆŽÐ, 48, 6, pp.48-52, June 1, 2003

#2003015
T. Sakurai, "Three big hedaches in 90 nm and below including Power-Aware Electronics ," Sequence Technology Summit 2003, Sequence, pp.10, June 1, 2003

#2003016
ėŒû@”Ž, _“c@_ˆę, –ėĢ@_ˆę, •ž•”@’叚, Danardono Dwi Antono, ŽR“c@‘å—T, ‹{č@—ēs, ˆîŠ_@ŒŦˆę, •―–{@r˜Y, ũˆä@‹MN, "IPÜFƒ[ƒVTH, FD-SOI‚ð—p‚Ē‚―’á“d—͍‚‘ŽVDDƒzƒbƒsƒ“ƒOƒvƒƒZƒbƒT," LSI IPƒfƒUƒCƒ“EƒAƒ[ƒh‰^‰cˆÏˆõ‰ï, June 10, 2003

#2003017
T. Sakurai, "ƒVƒXƒeƒ€LSI‚Ė‰Û‘č‚Æ“W–]," SONY“Á•Ęu‰‰, ‘åč, June 18, 2003

#2003018
T. Sakurai, "ƒVƒXƒeƒ€ƒCƒ“ƒpƒbƒP[ƒW‚ƃX[ƒp[ƒRƒlƒNƒg‚Ö‚ĖŠú‘Ō," “dŽqŽĀ‘•HŠwŒĪ‹†ŠiIMSI)‘‰ï, June 28, 2003

#2003019
T. Sakurai, "Reshaping EDA for Power," Design Automation Conference, USA(Anaheinm), 2, June 2003

#2003020
ũˆä‹MN, "Šî’ēu‰‰@SOCÝŒv‚Ė‰Û‘č‚ƈŲ‹ÆŽí˜AŒg‚É‚æ‚éƒ\ƒŠƒ…[ƒVƒ‡ƒ“," SoCÝŒv‹ZpƒtƒH[ƒ‰ƒ€2003, V‰Ą•l, pp.1-24, July 3, 2003

#2003021
ũˆä‹MN, "”ž“ą‘Ė‚ðŒĄˆø‚·‚éƒ}[ƒPƒbƒg‚Æ‹Zp-65nmLSI‚Ö‚ĖŠú‘Ō-," ‘æ20ŠúF‘æ1‰ņJSTƒtƒH[ƒ‰ƒ€, pp.1.1-1.18, July 14, 2003

#2003022
ũˆä‹MN, "“ž—ˆ‚·‚郆ƒrƒLƒ^ƒXEƒlƒbƒgƒ[ƒNŽÐ‰ï-65nmLSI‚Š‘ņ‚­V‚ĩ‚ĒĒŠE," ƒTƒCƒGƒ“ƒXƒtƒH[ƒ‰ƒ€, ŒãŠy‰€‰ïŠŲ, pp.109, July 14, 2003

#2003023
‹{č@—ēs, č{@MûG, ėŒû@”Ž, ũˆä ‹MN, "ƒfƒWƒ^ƒ‹‰Æ“d‚ÉŒü‚Ŋ‚―’჊[ƒN“d—̓fƒWƒ^ƒ‹‰ņ˜H‹Zp -Zigzag SCCMOS scheme-," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, ICD2003-39, pp.1-6, July 2003

#2003024
ŽOâ@’q, \ŽR@Œ\‰î, Ý’ˁ@r”V, “āŽR@–M’j, ‘Šâ@ˆę•v, ėŒû@”Ž, ũˆä@‹MN, "ƒ}ƒ‹ƒ`ƒ^ƒXƒNŽĀ‘•ƒ}ƒ‹ƒ`ƒƒfƒBƒA‚ɑ΂·‚éŽü”g”-“dŒđ“dˆģ‹Ķ’ēŒ^“d—͐§Œä," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, ICD2003-40, pp.7-12, July 2003

#2003025
ũˆä‹MN, "“ŪėŽžƒŠ[ƒNíŒļ@‰ņ˜H‚Đ‚įƒ\ƒtƒg‚܂ŘAŒg," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX“Á•Ę•ŌW”Å, pp.73-79, Aug. 2003

#2003026
‹{č—ēs, ũˆä‹MN, "ƒŠ[ƒN‚ð’áŒļ‚·‚ézigzag CMOS‚ĖŒŸ“Ē," STARCƒVƒ“ƒ|ƒWƒEƒ€2003, į—Ē, Sep. 11, 2003

#2003027
T.Someya,T. Sakurai, "Integration of Organic Filed-Effect Transistors and Rubbery Presssure Senso for Artificial Skin Applications," IEEE International Electron Devices Meeting, USA(Washington), pp.8.4.1-8.4.4, Sep. 12, 2003 (PDF)

#2003028
T. Sakurai, "For The LAST Time, Who Is Going To Solve The POWER Problem!," IEEE International Electron Devices Meeting, USA(Washington), 24, Sep. 12, 2003

#2003029
õ’J—ē•v, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚Ɖņ˜H‹Zpiĩ‘Ōu‰‰j," NPOƒT[ƒLƒbƒgƒlƒbƒgƒ[ƒN’č—á‰ï‡,, ‰ņ˜H‰ïŠŲ@“Œ‹ž, Sep. 19, 2003

#2003030
Fayez Robert Saliba, Takayasu Sakurai, "Low-Energy Flip-Flops Using Transistor Stack Effect," “dŽqî•ņ’ʐMŠw‰ï ƒ\ƒTƒCƒGƒeƒB‘å‰ï, VŠƒ‘åŠw, A-3. VLSI ÝŒv‹Zp, Sep. 23, 2003

#2003031
Yingxue Xu, Takayuki Miyazaki, Hiroshi Kawaguchi, Takayasu Sakurai, "Fast Block-Wise VDD-Hopping Scheme," “dŽqî•ņ’ʐMŠw‰ï2003”Nƒ\ƒTƒCƒGƒeƒB‘å‰ï, VŠƒ‘åŠw, A-3-11, Sep. 23, 2003 (PDF)

#2003032
“ŋ‰i˜aG, ‹{č—ēs, ũˆä‹MN, "’á“d—́Eƒ‰ƒCƒuƒ‰ƒŠĨƒZƒ‹‚Ė‘I‘ð‚ÉŠÖ‚·‚éˆęŒŸ“Ē," “dŽqî•ņ’ʐMŠw‰ïŠî‘bE‹ŦŠEƒ\ƒTƒCƒGƒeƒB‘å‰ï, VŠƒ‘åŠw, A-3-8, pp.58, Sep. 23, 2003

#2003033
‹S’ˍ_•―, ũˆä‹MN, "ƒ`ƒbƒvŠÔƒƒCƒ„ƒŒƒX“dŒđ“`‘—‚ÉŠÖ‚·‚錟“Ē," “dŽqî•ņ’ʐMŠw‰ï@2003”N Šî‘bE‹ŦŠEƒ\ƒTƒCƒGƒeƒB‘å‰ï, VŠƒ‘åŠw, A-1-3, pp.3, Sep. 25, 2003

#2003034
Î“cŒõˆę, ũˆä‹MN, "•‰ƒoƒCƒAƒX§ŒäƒXƒCƒbƒ`‚ð—p‚Ē‚―‚ļ“xƒXƒCƒbƒ`ƒgƒLƒƒƒpƒVƒ^‰ņ˜H," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒGƒeƒB‘å‰ï, VŠƒ‘åŠw, A-1-7, pp.7, Sep. 25, 2003

#2003035
‹{č—ēs, ũˆä‹MN, "ƒŠ[ƒN“d—ŽƒGƒ~ƒ…ƒŒ[ƒ^ -‚臒lƒfƒoƒCƒX‚É‚æ‚é’á臒lƒGƒ~ƒ…ƒŒ[ƒVƒ‡ƒ“-," “dŽqî•ņ’ʐMŠw‰ï 2003”NŠî‘bE‹ŦŠEƒ\ƒTƒCƒGƒeƒB‘å‰ï, VŠƒ‘åŠw, A-1-6, pp.6, Sep. 25, 2003

#2003036
Danardono Dwi Antono, Takayasu Sakurai, "Modeling of Inductive Interconnect Responses and Coupling Effects ," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, VŠƒ‘åŠw, SA-1-3, pp.S-4, Sep. 25, 2003 (PDF)

#2003038
ũˆä‹MN, "”ũŨ‰ŧ‚ÅŒĐ‚Ķ‚Ä‚Ŧ‚―LSIÝŒv‚Ė‹Zp“I‰Û‘č‡@," VLSI@Report, No.230, pp.6-8, Sep. 2003

#2003039
T. Sakurai, "(Invited)Perfective of Low Power Electronics," IEEE seminar on System on Chip: Design for Low power, France, Oct. 14, 2003

#2003040
T. Sakurai, "(Invited)System-on-a- Chip vs System-in-a-Package:design and interconnection issues," Advanced Metallization Conference(AMC)2003, Canada(Montreal), Oct. 21, 2003 (PDF)

#2003042
‹–@Œuá, ›Á@’ŋŠq, ‹{č@—ēs, ėŒû@”Ž, ũˆä@‹MN, "‚ƒŠ[ƒNŠÂ‹Ŧ‚É‚Ļ‚Ŋ‚éSelf-Timed Cut-Off–@‚ð—˜—p‚ĩ‚―“Œv“I‚ČƒŠ[ƒN“d—ŽíŒļŽč–@," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, DSP2003-135, ICD2003-133, IE2003-95, pp.65-70, Oct. 2003

#2003043
Fayez Robert Saliba, Kyeong-Sik Min, ėŒû@”Ž, _“c@_ˆę, ũˆä@‹MN, "ƒTƒu1V‚ĖSRAM‚É‚Ļ‚Ŋ‚郊[ƒN‚ð2Œ…ˆČãíŒļ‚·‚éVŽč–@RRDSV," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, DSP2003-136, ICD2003-134, IE2003-96, pp.71-76, Oct. 2003

#2003044
ũˆä‹MN, "”ũŨ‰ŧ‚ÅŒĐ‚Ķ‚Ä‚Ŧ‚―LSIÝŒv‚Ė‹Zp“I‰Û‘č‡A," VLSI@Report, No.231, pp.6-8, Oct. 2003

#2003045
H. Im, T.Inukai, H.Gomyo, T.Hiramoto, T. Sakurai , "VTCMOS Characterisitics and Its Optimum Conditions Predicated By a Compact Analytical Model," IEEE Transaction‚“ on very large sacale intagration(VLSI) Systems, Vol.Vol.11, No.No.5, pp.755-761, Oct. 2003

#2003046
õ’J—ē•v, ũˆä‹MN, "–ē‚ð‚Đ‚―‚ŋ‚ɁEEEEŽĀŒŧ‚É’§‚Þ—L‹@”ž“ą‘ĖŠJ”­‚ĖÅV“ŪŒü"i“Á•Ęu‰‰j," , uŽĀ‘•‹Zpƒ[ƒhƒ}ƒbƒv 2003(JEITA)•ņvŒöŠJu‰‰‰ï, ‰ņ˜H‰ïŠŲ@“Œ‹ž, Nov. 10, 2003

#2003047
ũˆä‹MN, "ƒVƒXƒeƒ€ƒCƒ“ƒpƒbƒP[ƒW‚ƃX[ƒp[ƒRƒlƒNƒg‚Ö‚ĖŠú‘Ō," ‘æ4‰ņuƒvƒŠƒ“ƒg‰ņ˜HÝŒvŽŌ‚Ė‚―‚ß‚ĖÝŒvƒZƒ~ƒi[v, ‰ņ˜H‰ïŠŲ@’n‰šˆęŠK‰ï‹cŽš, Nov. 11, 2003 (PDF)

#2003048
õ’J—ē•v, ũˆä‹MN, "—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ƏWÏ‰ņ˜Hiĩ‘Ōu‰‰j," ‰ž—p“dŽq•ĻŦ•Š‰Č‰ïŽE“‡’ÐŧėŠŠÖžŽxŽÐƒ}ƒ‹ƒ`ƒz[ƒ‹, ‘åã, ‘æ9ŠŠ@‘æ5†, pp.241-246, Nov. 12, 2003

#2003049
õ’J—ē•v, ũˆä‹MN, "‰îŒė‚ĖŽč‘Ŧ‚Æ‚Č‚éƒ]," ŽYŒoV•·, Nov. 22, 2003

#2003050
õ’J—ē•v, ũˆä‹MN, "æ’[‹Zpuƒqƒgv‚É“ũ”–," ’Đ“úV•·, Nov. 22, 2003

#2003051
õ’J—ē•v, ũˆä‹MN, "ƒƒ{ƒbƒgŽčG‚čŠī’m," “ú–{ŒoÏV•·, Nov. 24, 2003

#2003052
õ’J—ē•v, ũˆä‹MN, "—L‹@‘fŽq‚Å‘@Ũ‚ģŽĀŒŧ," “úŠ§H‹ÆV•·, Nov. 25, 2003

#2003053
õ’J—ē•v, ũˆä‹MN, "lH”į•†@2-3ƒ~ƒŠ–ˆ‚ÉŠīˆģ“_," “ú–{H‹ÆV•·, Nov. 25, 2003

#2003054
ũˆä‹MN, "ƒTƒu100nmLSIŽĀ—p‰ŧ‚ÉŒü‚Ŋ‚―^‚Ė‹Zp‰Û‘č‚ð’T‚é," ‘æ7‰ņƒVƒXƒeƒ€ƒ[ƒNƒVƒ‡ƒbƒv, –k‹ãB, pp.169-, Nov. 26, 2003

#2003055
õ’J—ē•v, ũˆä‹MN, "S‚ā“`‚í‚éH”į•†ŠīŠo‚ ‚郍ƒ{ƒbƒgŠJ”­," “Œ‹žV•·, Dec. 2, 2003

#2003056
ũˆä‹MN, "Ü‚č‹Č‚°‰Â”\‚ȐlH”į•†—L‹@ƒgƒ‰ƒ“ƒWƒXƒ^‚ÅŽĀŒŧ," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, pp.32, Dec. 8, 2003

#2003057
õ’J—ē•v, ũˆä‹MN, "—L‹@”ž“ą‘Ė‚ĖV—Ėˆæ‚ðŠJ‘ņ," “úŠ§H‹ÆV•·, Dec. 12, 2003

#2003058
ũˆä‹MN, •―–{r˜Y, Ž–ėŽ›Gr, "‹É’áÁ”ï“d—́EVƒVƒXƒeƒ€LSI‹Zp‚ĖŠJ”­," ƒVƒŠƒRƒ“’īWÏ‰ŧƒVƒXƒeƒ€‘å165ˆÏˆõ‰ï, OÏ‰ïŠŲ, pp.1-11, Dec. 19, 2003

#2003059
ũˆä‹MN, "ƒXƒP[ƒŠƒ“ƒO‚ģ‚ę‚―’ī‚Ŧ”\‰ņ˜H‚ƃXƒP[ƒŠƒ“ƒOˆČŠO‚Å‚ĖV‹@”\“ą“ü," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, 2003/12/22†, pp.67, Dec. 22, 2003

#2003060
ũˆä‹MN, "“dŽqlH”į•†‚ĖŠJ”­@OTFT‚Å“dŽqlH”į•†‚ðŠJ”­@Šų‘ķ‹Zp‚Å’áƒRƒXƒg‰ŧ‚āŽĀŒŧ," Electronic Journal, 12ŒŽ†, pp.61, Dec. 2003

#2003061
J. H. Choi, T. Sakurai, "Statistical Leakage Current Reduction by Self-Timed Cut-Off Scheme for High Leakage Environments," IEEE Custom Integrated Circuits Conference, USA(San Jose), 28.3, Sep. 24, 2003

#2003062
K. Min, K. Kanda, T. Sakurai,, "Row-by-row dynamic source-line voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's ," IEEE/ACM International Symposium on Low Power Electronics and Design,, Seoul, pp.66-71, Aug. 25-27, 2003

2002

#2002001
H. Kawaguchi, G. Zhang, S. Lee, Y. Shin, and T. Sakurai, "A Controller LSI for Realizing Vdd-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System," IEICE Transactions on Electronics, Vol.E85-C, No.2, pp.263-271, Feb. 2002 (PDF)

#2002002
T. Sakurai, "Low-power and High-Speed V VLSI Design with Low Supple Voltage Through Cooperation between Levels(Invited)," IEEE International Symposium on Quality Electronic Design, San Jose, CA, USA, 4A, pp.445-450, Mar. 2002

#2002003
K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakura, "VTH-Hopping Scheme to Reduce Subthreshold Leakage for Low-Power Processors," IEEE Journal of Solid-State Circuits, Vol.37, No.3, pp.413-419, Mar. 2002 (PDF)

#2002004
D. D. Antono and T. Sakurai, "Transmission Line Models and Overshoots of On-chip Interconnects," “dŽqî•ņ’ʐMŠw‰ï ‘‡‘å‰ï, A-3-22, Mar. 2002 (PDF)

#2002005
ŽR“c‘å—T, ũˆä‹MN, "ƒoƒXƒVƒƒƒtƒŠƒ“ƒO‚É‚æ‚éƒIƒ“ƒ`ƒbƒvƒoƒX‚Ė’áÁ”ï“d—͉ŧ(Bus shuffling for on-chip buses in low-power application-specific systems)," “dŽqî•ņ’ʐMŠw‰ï ‘‡‘å‰ï, A-3-5, Mar. 2002

#2002006
T. Sakurai, "Low-Power LSI -Through cooperation among levels-," Germany-Japan Information Technology Forum, Birlinghoven/Windhagen, Germany, 2, Apr. 2002 (PDF)(PDF2)

#2002007
ũˆä‹MN, "LSI‚ĖV‹Ŧ’n‚ðŠJ‚­ƒX[ƒp[ƒRƒlƒNƒg," •\–Ę‹Zp2002, 53, 4, pp.224-227, Apr. 2002

#2002008
ũˆä‹MN, "ƒ\ƒtƒgƒEƒGƒAEƒn[ƒhƒEƒGƒA‚Ė˜AŒg‚É‚æ‚éSuperH‚Ė’áÁ”ï“d—͉ŧ," ‘æ1‰ņSuperHƒI[ƒvƒ“ƒtƒH[ƒ‰ƒ€, pp.1-16, May 2002

#2002009
ėŒû”Ž, h‰pŸŠ, ũˆä‹MN, "IP—DGÜFu75%“d—͐ߌļ‰Â”\‚Č—ĢŽUFV§Œä‹@\‚ð—L‚·‚é’á“d—̓ŠƒAƒ‹ƒ^ƒCƒ€OSFƒĘITRON-LPv," LSI IPƒfƒUƒCƒ“EƒAƒ[ƒh‰^‰cˆÏˆõ‰ï, ˆÏˆõ’·F“c’†@š“ņiā’c–@l‘Û’ī“d“ąŽY‹Æ‹ZpŒĪ‹†ƒZƒ“ƒ^[•›—Ž–’·, ’ī“d“ąHŠwŒĪ‹†ŠŠ’·j, •›ÜFŒĪ‹†•Ž‹ā150–œ‰~, May 2002 (PDF)

#2002010
S. Hattori and T. Sakurai, "90% Write Power Saving SRAM Using Sense-Amplifying Memory Cell," Symposium on VLSI Circuits, Honolulu, HI, USA, 4.2, pp.46-47, June 2002 (PDF)

#2002011
T. Sakurai, "Achieving Low-Power LSI Through Cooperation Among Levels," Special Seminar, Dept. of EE, Univ. of Hawaii, Honolulu, HI, USA, June 2002

#2002012
Y. Shin and T. Sakurai, "Power Distribution Analysis of VLSI Interconnects Using Model Order Reduction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.21, No.6, pp.739-745, June 2002 (PDF)

#2002013
T. Sakurai, "‘“ā‹ZpŒĪ‹†ŽŌ‚Đ‚įŒĐ‚―“ú–{LSI“ŪŒü," SLI seminar, July 2002

#2002014
ũˆä‹MN, "“ŪėŽžƒŠ[ƒNíŒļ@‰ņ˜H‚Đ‚įƒ\ƒtƒg‚܂ŘAŒg," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX8ŒŽ†, pp.59-70, Aug. 2002

#2002015
K. Nose and T. Sakurai, "Power-Conscious Interconnect Buffer Optimization with Improved Modeling of Driver MOSFET and Its Implications to Bulk and SOI CMOS Technology," International Symposium on Low Power Electronics and Design, Monterey, CA, USA, 1.4s, pp.24-29, Aug. 2002 (PDF)

#2002016
_“c_ˆę, ‹{č—ēs, •ž•”’叚, ũˆä‹MN, "ƒZƒ“ƒXƒAƒ“ƒvŒ^ƒƒ‚ƒŠƒZƒ‹‚ð—p‚Ē‚―SRAM‘‚Ŧž‚Ý“d—Í‚ĖíŒļ•ûŽŪ," “dŽqî•ņ’ʐMŠw‰ï WÏ‰ņ˜HŒĪ‹†‰ï, ”ŸŠŲ, pp.65-70, Aug. 2002

#2002017
K. Kanda, T. Miyazaki, M. Kyeong Sik, H. Kawaguchi, and T. Sakurai, "Two Orders of Magnitude Leakage Power Reduction of Low Voltage SRAM's by Row-by-Row Dynamic VDD Control (RRDV) Scheme," IEEE ASIC/SOC conference, Rochester, NY, USA, FB2, pp.381-385, Sep. 2002

#2002018
T. Sakurai, "Minimizing Power Across Multiple Technology and Design Levels(Invited)," International Conference on Computer Aided Design, San Jose, CA, USA, 1B.1, pp.24-27, Nov. 2002

#2002019
ũˆä‹MN, "SoC‚ĖŒŧó‚ƏŦ—ˆ“ŪŒü," EDN12ŒŽ†, pp.70-77, Dec. 2002

#2002020
ũˆä‹MN, "ƒX[ƒp[ƒRƒlƒNƒg‹Zp‚ĖŒŧó‚ƏŦ—ˆ," ‘æ3‰ņASET‘―‘w”zü‹ZpƒtƒH[ƒ‰ƒ€, pp.47-69, Dec. 2002

#2002021
_“c_ˆę, ‹{č—ēs, č{MûG, ũˆä‹MN, "s’PˆĘ‚Å‚Ė“dŒđ“dˆģ§Œä(RRDV)‚ð—p‚Ē‚―SRAM‚ĖƒŠ[ƒN“d—͍íŒļŽč–@- 0.5VĒ‘ã‚Ė‚‘ŽSRAM‚ð–ÚŽw‚ĩ‚Ä -," “dŽqî•ņ’ʐMŠw‰ï WÏ‰ņ˜HŒĪ‹†‰ï, ŒF–{, pp.7-12, Dec. 2002

#2002022
S. S. Lee, S. J. Lee, and T. Sakurai, "Energy-Constrained VDD/VTH Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems," Journal of Circuits, Systems and Computers, Vol.11, No.6, pp.611-620, Dec. 2002 (PDF)

#2002023
H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, and T. Sakurai, "A 0.5-V, 400-MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 6.3, pp.108-109, Feb. 2003

#2002024
K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 10.7, pp.186-187, Feb. 2003

#2002025
K. S. Min and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 22.8, pp.400-401, Feb. 2003 (PDF)

#2002026
T. Sakurai, "Perspectives on Power-Aware Electronics (Plenary Talk, Invited)," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 1.2, pp.26-29, Feb. 2003

#2002027
ũˆä‹MN, "ƒVƒXƒeƒ€ƒCƒ“ƒpƒbƒP[ƒW‚ĖŠú‘Ō," NorthŽĀ‘•‹ZpƒZƒ~ƒi[, ƒzƒeƒ‹ƒƒgƒƒ|ƒŠƒ^ƒ“, Feb. 2003

#2002028
K. Kanda and T. Sakurai, "Low-Power High-Speed Circuit Design for VLSI Memory Systems," Doctor Dissertation, Feb. 2003 (PDF)

#2002029
ŽR“c‘å—T, ũˆä‹MN, "V‹KƒAƒ‹ƒSƒŠƒYƒ€‚ðŽg—p‚ĩ‚―•Ą”‚ĖƒAƒvƒŠƒP[ƒVƒ‡ƒ“‰š‚Å‚ĖƒoƒXƒVƒƒƒtƒŠƒ“ƒO‚É‚æ‚éƒIƒ“ƒ`ƒbƒvƒoƒX‚ĖÁ”ï“d—͍íŒļ," “dŽqî•ņ’ʐMŠw‰ï‘‡‘å‰ï, A-3-4, Sep. 2002

#2002030
D. D. Antono and T. Sakurai, "Modeling of Inductive Interconnect Responses and Coupling Effects in Deep-Submicron VLSI," Master Dissertation, Feb. 2003 (PDF)

#2002031
Q. Liu, T. Sakurai, and T. Hiramoto, "Optimum Device Consideration for@Standby Power Reduction Scheme Using Drain Induced Barrier Lowering (DIBL)," International Conference on Solid State Devices and Materials, Nagoya Congress Center, pp.258-259, Sep. 2002

#2002032
ŽR“c‘å—T, ũˆä‹MN, "ƒoƒXƒVƒƒƒtƒŠƒ“ƒO‚Æ‚ŧ‚ĖŠg’Ģ‚ÉŠÖ‚·‚闝˜_“I‹y‚ŅŽĀŒą“IlŽ@," CŽm˜_•ķ, “Œ‹ž‘åŠw, Feb. 2002

#2002033
K. Aisaka, T. Aritsuka, S. Misaka, K. Toyama, K. Uchiyama, K. Ishibashi, H. Kawaguchi, and T. Sakurai, "Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 Decoder," Symposium on VLSI Circuits, pp.216-217, June 2002 (PDF)

#2002034
J. Goodman, T. Sakurai, D. Buss, and T. Suga, "SOC (System-on-a-chip) versus SIP (System-in-a-package)," Symposium on VLSI Circuits, Panel discussion, pp.96, June 2002 (PDF)

#2002035
ũˆä‹MN, "–{‰đ‚ÅŒę‚鍡Œã‚Ė”ž“ą‘Ė‹Zpí—Š@d—vƒAƒvƒŠƒP[ƒVƒ‡ƒ“‚ƃL[‹Zp," JST ƒtƒH[ƒ‰ƒ€, ŒãŠy‰€‰ïŠŲ, pp.‡V-1-6, Jan. 16, 2003

#2002036
ũˆä‹MN, "Åæ’[ƒVƒXƒeƒ€LSI‚ĖŒŧó‚Ɖۑč," “dŽqEî•ņ‹Zpƒ[ƒNƒVƒ‡ƒbƒv, q‹ó‰ïŠŲ, pp.38-55, Jan. 14, 2003

2001

#2001001
T. Sakurai, "Low Power Design of Digital Circuits," International Symposium on Key Technologies for Future VLSI Systems, pp.1-5, Jan. 2001 (PDF)

#2001002
ũˆä‹MN, "‹É’áÁ”ï“d—́EVƒVƒXƒeƒ€LSI‚ĖŠJ‘ņ," ’īWÏ‰ŧƒfƒoƒCƒXEƒVƒXƒeƒ€‘æ165ˆÏˆõ‰ï ‘æ19‰ņŒĪ‹†‰ïŽ‘—ŋ, pp.1-15, Apr. 10, 2001 (PDF)

#2001003
T. Sakurai, "VLSI design challenges and EDA in the forthcoming decade," DA SHOW 2001 TOKYO, July 17, 2001 (PDF)

#2001004
ũˆä‹MN, "ƒX[ƒp[ƒRƒlƒNƒg‚ɑΉž‚ĩ‚―‘wŠÔÚ‘ąƒvƒƒZƒX," ŽĀ‘•ƒvƒƒZƒXHŠwƒVƒ“ƒ|ƒWƒEƒ€, May 18, 2001 (PDF)(PDF2)

#2001005
T. Sakurai, "Recent Topics for Realizing Low-Power, High-Speed VLSI's," International Symposium on Advanced CMOS Devices, pp.17-22, Oct. 31, 2001 (PDF)(PDF2)

#2001006
ũˆä‹MN, "‚ą‚ę‚Đ‚į‚ĖŒĪ‹†ŠJ”­‚É‹‚ß‚į‚ę‚é‚ą‚Æ," NEDO ƒtƒH[ƒ‰ƒ€2001ƒeƒNƒjƒJƒ‹ƒZƒbƒVƒ‡ƒ“, Sep. 20, 2001 (PDF)

#2001007
T. Sakurai, "Issues of Current LSI Technology and an Expectation for New System-Level Integration," International Conference on Solid State Devices and Materials, pp.36-37, Sep. 2001 (PDF)(PDF2)

#2001008
T. Sakurai, "Perspective of VLSI in the year 2010 and beyond? From a designer's point of view," JSAP International No.3, pp.15-21, Jan. 2001 (PDF)

#2001009
T. Sakurai, "Panel on Low-Voltage Design or the End of CMOS Scaling?," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, Evening Session, Feb. 2002 (PDF)

#2001010
ũˆä‹MN, "DSM”zü‚ƃX[ƒp[ƒRƒlƒNƒg‚Ö‚ĖŠú‘Ō," “dŽqî•ņ’ʐMŠw‰ï‹Zp•ņ‘, ƒfƒUƒCƒ“ƒKƒCƒ„, pp.15-20, Nov. 28, 2001 (PDF)

#2001011
ũˆä‹MN, "”ž“ą‘Ė•œŠˆ‚ÉŒü‚Ŋ‚―ˆŲ‹ÆŽí˜AŒg‚É‚æ‚éŽYŠw‹Ī“ŊŒĪ‹†," CCRƒVƒ“ƒ|ƒWƒEƒ€, “Œ‹ž, Dec. 7, 2001 (PDF)

#2001012
H. Im, T. Inukai, H. Gomyo, T. Hiramoto, and T. Sakurai, "VTCMOS Characteristics and Its Optimum Conditions Predicted by a Compact Analytical Model," International Symposium on Low Power Electronics and Design, pp.123-128, Aug. 2001 (PDF)(PDF2)

#2001013
T. Inukai, T. Hiramoto, and T. Sakurai, "Variable Threshold Voltage CMOS (VTCMOS) in Series Connected Circuits," International Symposium on Low Power Electronics and Design, pp.201-206, Aug. 2001 (PDF)(PDF2)

#2001014
Y. Shin and T. Sakrai, "Estimation of Power Distribution in VLSI Interconnects," International Symposium on Low Power Electronics and Design, pp.370-375, Aug. 2001 (PDF)

#2001015
M. Hirabayashi and T. Sakurai, "Design Methodology and Optimization Strategy for Dual-VTH Scheme using Commercially Available Tools," International Symposium on Low Power Electronics and Design, pp.283-286, Aug. 2001 (PDF)

#2001016
D. D. Antono, T. Sakurai, "Inductance Effect on VLSI Interconnections," “dŽqî•ņ’ʐMŠw‰ï 2001”NŠî‘bE‹ŦŠEƒ\ƒTƒCƒGƒeƒB‘å‰ï, pp.61, Sep. 18, 2001 (PDF)

#2001017
ũˆä‹MN, "•~‹‚Ė’á‚ĒTLO‚ð–ÚŽw‚ĩ‚Ä," ŽYŠwŠŊ˜AŒgŽx‰‡ƒ}ƒKƒWƒ“ InterLab, 36, pp.31-36, Oct. 2001 (PDF)

#2001018
ŽR“c‘å—T, h ‰pŸŠ, ėŒû ”Ž, ũˆä‹MN, "Bus Shuffling ’áÁ”ï“d—ÍŒü‚Ŋ‚ĖV‚ĩ‚ĒƒoƒX‹Zp," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ MŠw‹Z•ņICD2001-65`78, 101, 266, pp.1-8, Aug. 24, 2001 (PDF)

#2001019
K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakurai, "VTH-hopping scheme for 82% power saving in low-voltage processors," IEEE Custom Integrated Circuits Conference, pp.93-96, May 2001 (PDF)

#2001020
–ėĢ_ˆę, •―—Ņ‰ë”V, ėŒû”Ž, —›―ŸŠ, ũˆä‹MN, "臒lƒzƒbƒsƒ“ƒO(VTH-hopping)Žč–@‚ð—p‚Ē‚―’á“dˆģE’áÁ”ï“d—̓vƒƒZƒbƒT," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ MŠw‹Z•ņICD2001-33, 2001 (PDF)

#2001021
K. Nose and T. Sakurai, "Two schemes to reduce interconnect delay in bi-directional and uni-directional buses," Symposium on VLSI Circuits, pp.193-194, June 2001 (PDF)

#2001022
K. Nose and T. Sakurai, "Current sensing device for micro-IDDQ test," Electronics and Communications in Japan part 2, 84, 9, May 2001 (PDF)

#2001023
H. Kawaguchi, G. Zhang, S. Lee, and T. Sakurai, "An LSI for VDD-Hopping and MPEG4 System Based on the Chip," IEEE International Symposium on Circuit and Systems, pp.918-921, May 2001 (PDF)

#2001024
ėŒû ”Ž, ’Ģ j, —› ―ŸŠ, h ‰pŸŠ, ũˆä ‹MN, "’á“d—ÍŽĀŽžŠÔ‘gžƒVƒXƒeƒ€‚Ė‚―‚ß‚ĖOS, ƒAƒvƒŠƒP[ƒVƒ‡ƒ“, ƒn[ƒhƒEƒFƒA‹Ķ’ē‚É‚æ‚éCVS(Cooperative Voltage Scaling)‚Æ“dˆģƒzƒbƒsƒ“ƒO," “dŽqî•ņ’ʐMŠw‰ï ‹ZpŒĪ‹†•ņ ICD2001-32, pp.59-65, May 2001 (PDF)

#2001025
H. Kawaguchi, Y. Shin, and T. Sakurai, "Experimental Evaluation of Cooperative Voltage Scaling (CVS): A Case Study," IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp.17-23, Feb. 2001 (PDF)

#2001026
ũˆä‹MN, •―–{r˜Y, "‹É’áÁ”ï“d—́EVƒVƒXƒeƒ€LSI‹Zp‚ĖŠJ‘ņ," –Ē—ˆŠJ‘ņŠwpŒĪ‹†„iŽ–‹ÆŒĪ‹†ƒvƒƒWƒFƒNƒg‚ĖÐ‰î, 2001

#2001027
ėŒû”Ž, ’Ģj, —›―ŸŠ, ũˆä‹MN, "IP—DGÜFu"“dˆģƒzƒbƒsƒ“ƒO‚ƃAƒvƒŠƒP[ƒVƒ‡ƒ“ƒXƒ‰ƒCƒVƒ“ƒO‚É‚æ‚郊ƒAƒ‹ƒ^ƒCƒ€ƒAƒvƒŠƒP[ƒVƒ‡ƒ“Œü‚Ŋ’á“d—̓vƒƒZƒTƒVƒXƒeƒ€v," LSI IPƒfƒUƒCƒ“EƒAƒ[ƒh‰^‰cˆÏˆõ‰ï, ˆÏˆõ’·F“c’† š“ņiā’c–@l‘Û’ī“d“ąŽY‹Æ‹ZpŒĪ‹†ƒZƒ“ƒ^[•›—Ž–’· ’ī“d“ąHŠwŒĪ‹†ŠŠ’·j, •›ÜFŒĪ‹†•Ž‹ā150–œ‰~, Mar. 2001 (PDF)

#2001028
ŒĒŽ” ‹MŽm, ‚‹{ ^, Ž‰F—… Š°, Œã–ūŠ°”V, ėŒû”Ž, ũˆä ‹MN, •―–{ r˜Y, "High-Speedƒ‚[ƒhVTCMOS‚Æ‚ŧ‚ĖƒXƒP[ƒ‰ƒrƒŠƒeƒB," 2001”Nt‹G‘æ48‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, –ūŽĄ‘åŠw(“Œ‹ž), 29a-B-8, Sep. 2001 (PDF)

#2001029
ŒĒŽ” ‹MŽm, ũˆä ‹MN, •―–{ r˜Y, "cÏ‚݉ņ˜H‚É‚Ļ‚Ŋ‚éVTCMOS‚ĖÅ“KÝŒv," 2001”NH‹G‘æ62‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ï, ˆĪ’mH‹Æ‘åŠw(ˆĪ’m), Mar. 2001 (PDF)

#2001030
Hyunsik Im, T. Inukai, H. Gomyo, T. Sakurai, and T. Hiramoto, "Study of VTCMOS characteristics and its optimum conditions with a compact analytical model," 2001”Nt‹G‘æ48‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, –ūŽĄ‘åŠw(“Œ‹ž), 29a-B-9, Sep. 2001 (PDF)

#2001031
Hyunsik Im, T. Inukai, T. Sakurai, and T. Hiramoto, "Study of Short Channel Effect on the characteristics of a VTCMOS," 2001”NH‹G‘æ62‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ï, ˆĪ’mH‹Æ‘åŠw(ˆĪ’m), Sep. 21, 2001 (PDF)

#2001032
•ž•” ’叚, ũˆä ‹MN, "’áU•ƒrƒbƒgü•ûŽŪ‚ð—p‚Ē‚―’áÁ”ï“d—͍‚‘ŽSRAM," “dŽqî•ņ’ʐMŠw‰ï ƒGƒŒƒNƒgƒƒjƒNƒXƒ\ƒTƒCƒGƒeƒB‘å‰ï, C-12-38, pp.99, Sep. 14, 2001 (PDF)

#2001033
•ž•”’叚, _“c_ˆę, ũˆä‹MN, "‚‘ŽƒŒƒxƒ‹ƒRƒ“ƒo[ƒ^," ‰ž—p•Ļ—Šw‰ï Šwpu‰‰‰ï, pp.703, Feb. 2001 (PDF)

#2001034
ũˆä‹MN, "”ž“ą‘ĖŠJ”­ŒĪ‹†‚Ė‚ ‚č•û," FEDƒTƒƒ“, Oct. 2001

#2001035
T. Sakurai, "VLSI design challenges in the forthcoming decade - What may hinder design closure- (invited)," Design closure forum, pp.3.1-3.49, July 2001 (PDF)

#2001036
_“c_ˆę, ƒOƒGƒ“ ƒhƒDƒbƒN ƒ~ƒ“, ėŒû”Ž, ũˆä‹MN, "’áƒXƒ^ƒ“ƒoƒC“d—ŽSRAM‚Ė‚―‚ß‚ĖˆŲíƒŠ[ƒN“d—Ž—}§•ûŽŪ," ŒŽŠ§ƒfƒBƒXƒvƒŒƒC ("˜b‘č‚ĖƒfƒBƒXƒvƒŒƒC‚ÆŽü•Ó‰ņ˜H‹Zp"‚Ė’†‚ÅŒfÚ), pp.48-53, Oct. 2001 (PDF)

#2001037
K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, "Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's," IEEE Journal of Solid-State Circuits, Vol.36, No.10, pp.1559-1564, Oct. 2001 (PDF)

#2001038
_“c_ˆę, ƒOƒGƒ“ ƒhƒDƒbƒN ƒ~ƒ“, ėŒû”Ž, ũˆä‹MN, "’áƒXƒ^ƒ“ƒoƒC“d—ŽSRAM‚Ė‚―‚ß‚ĖˆŲíƒŠ[ƒN“d—Ž—}§•ûŽŪ," VDECƒfƒUƒCƒi[ƒYƒtƒH[ƒ‰ƒ€, Aug. 2001 (PDF)

#2001039
ũˆä‹MN, "Å‹ß‚ĖVLSIÝŒv‚Ė‰Û‘č‚Æ‚ŧ‚Ė‰ð–@|’áÁ”ï“d—͐݌v‹Zp‚𒆐S‚Ɂ|iĩ‘Ōj," Å‹ß‚ĖVLSIÝŒv‚Ė‰Û‘č‚Æ‚ŧ‚Ė‰ð–@u‰‰‰ï, ‰Ŧƒqƒ…[ƒ}ƒ“ƒlƒbƒgƒ[ƒN, u‹`No11, pp.1-52, Nov. 2001

#2001040
ũˆä‹MN, "2010”N‚ÉŒü‚Ŋ‚Ä‚ĖƒVƒXƒeƒ€LSI‚Ė‰Û‘č‚Æ“W–]iĩ‘Ōj," Re-Generation 21Advanced Course, ƒ\ƒj[ƒqƒ…[ƒ}ƒ“ƒLƒƒƒsƒ^ƒ‹‡ŠƒeƒNƒmƒƒW[ŒĪC•”, pp.1-163, June 2001

#2001041
ũˆä‹MN, "ƒX[ƒp[ƒRƒlƒNƒg V‚―‚ČƒGƒŒƒNƒgƒƒjƒNƒXŽY‹Æ‚ðØ‚čŠJ‚­ƒpƒbƒP[ƒWŽĀ‘•ŽY‹Æ‹Zp," Breakthrough, ƒŠƒAƒ‰ƒCƒYŽÐ, Dec. 2001 (PDF)

#2001042
T. Sakurai, "Superconnect Technology (invited)," IEICE Transactions on Electronics, Vol.E84/C12, No., pp.1709-1716, June 2001 (PDF)

#2001043
_“c_ˆę, ƒOƒGƒ“EƒhƒDƒbƒNEƒ~ƒ“, ėŒû ”Ž, ũˆä‹MN, "’áƒXƒ^ƒ“ƒoƒC“d—ŽSRAM‚Ė‚―‚ß‚ĖˆŲíƒŠ[ƒN“d—Ž—}§•ûŽŪ," “dŽqÞ—ŋi“ÁW"’áÁ”ï“d—͉ŧi‚Þ”ž“ą‘ĖƒfƒoƒCƒX"‚Ė’†‚ÅŒfÚj, pp.24-28, Apr. 2001 (PDF)

#2001044
_“c_ˆę, ƒOƒGƒ“ ƒhƒDƒbƒN ƒ~ƒ“, ėŒû ”Ž, ũˆä‹MN, "’áƒXƒ^ƒ“ƒoƒC“d—ŽSRAM‚Ė‚―‚ß‚ĖˆŲíƒŠ[ƒN“d—Ž—}§•ûŽŪ," “dŽqî•ņ’ʐMŠw‰ï WÏ‰ņ˜HŒĪ‹†‰ï, pp.21-25, Dec. 2001 (PDF)

#2001045
–ėĢ_ˆę, ũˆä‹MN, "Circuit Design for Low-Power High-Speed VLSI Processorin 0.5V Generation (0.5VĒ‘ã‚Ė’á“d—́E‚‘ŽVLSIƒvƒƒZƒbƒT‚ðŽuŒü‚ĩ‚―‰ņ˜HÝŒv)," ”ŽŽm˜_•ķ, Tokyo Univ., 2001 (PDF)

#2001046
ũˆä‹MN, "“ú–{‚Ė”ž“ą‘ĖÄ‹ŧ‚Ė‚―‚ß‚É- ÝŒvŽŌ‚Ė—§ę‚Đ‚į -," “ú–{‚Ė”ž“ą‘Ė‚ðŒę‚é‰ï, Aug. 2001

#2001047
•ž•”’叚, ũˆä‹MN, "Low-Power SRAM Design using Low-Voltage and Low-Swing Techniques," CŽm˜_•ķ, “Œ‹ž‘åŠw, Feb. 2002 (PDF)

2000

#2000001
ó–ė—Y‘ū˜Y, ũˆä‹MN, "AdiabaticŒī—‚ð—p‚Ē‚―CMOS‰ņ˜H—pƒNƒƒbƒNƒWƒFƒlƒŒ[ƒ^," CŽm˜_•ķ, “Œ‹ž‘åŠw, Mar. 2000 (PDF)

#2000002
’Ģj, ũˆä‹MN, "VDDƒzƒbƒsƒ“ƒOVLSI—pƒNƒƒbƒN”­ķ‰ņ˜H‚ÆDC-DCƒRƒ“ƒo[ƒ^‚ĖŒĪ‹†," CŽm˜_•ķ, “Œ‹ž‘åŠw, Mar. 2000 (PDF)

#2000003
•―—Ņ‰ë”V, ũˆä‹MN, "’áÁ”ï“d—͍‚Ŧ”\ƒvƒƒZƒbƒT‚ÉŠÖ‚·‚éŒĪ‹†," CŽm˜_•ķ, “Œ‹ž‘åŠw, Mar. 2000 (PDF)

#2000004
ũˆä‹MN, "ƒVƒXƒeƒ€LSIÝŒv‚ĖŒŧó‚Ɖۑč," î•ņˆ—Šw‰ï˜_•ķŽ, 41, 4, Apr. 2000 (PDF)

#2000005
–ėĢ_ˆę, ũˆä‹MN, "ƒ}ƒCƒNƒIDDQƒeƒXƒg‚Ė‚―‚ß‚Ė“d—Ž‘Š’čƒfƒoƒCƒX," “dŽqî•ņ’ʐMŠw‰ï˜_•ķŽ, J83-C, 6, pp.516-522, June 2000 (PDF)

#2000006
K. Nose, and T. Sakurai, "Analysis and Future Trend of Short-Circuit Power," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.19, No.9, pp.1023-1030, Sep. 2000 (PDF)

#2000007
H. Kawaguchi, K. Nose, and T. Sakurai, "A Super Cut-off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-by Current," IEEE Journal of Solid-State Circuits, Vol.35, No.10, pp.1498-1501, Oct. 2000 (PDF)

#2000008
Y. Shin, K. Choi, and T. Sakurai, "Power-Conscious Scheduling for Real-Time Embedded Systems Design," An International Journal of Custom-Chip Design, Simulation, and Testing, Vol., No., 2001 (PDF)

#2000009
ũˆä‹MN, "ƒX[ƒp[ƒRƒlƒNƒg‹Zp‚ƃOƒ[ƒoƒ‹ƒCƒ“ƒeƒOƒŒ[ƒVƒ‡ƒ“iŠî’ēu‰‰j," ‰ž—p•Ļ—Šw‰ï ƒVƒŠƒRƒ“ƒeƒNƒmƒƒW[‘æ23‰ņŒĪ‹†‰ï, Nov. 2000

#2000010
T. Sakurai, "Design Challenges for 0.1um and Beyond," Asia and South Pacific Design Automation Conference, pp.553-558, Jan. 2000 (PDF)

#2000011
S. Lee, and T. Sakurai, "Run-Time Power Control Scheme Using Software Feedback Loop for Low-Power Real-Time Applications," Asia and South Pacific Design Automation Conference, pp.381-386, Jan. 2000 (PDF)

#2000012
N. D. Minh, and T. Sakurai, "Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies," Asia and South Pacific Design Automation Conference, pp.475-480, Jan. 2000 (PDF)

#2000013
K. Nose, and T. Sakurai, "Optimization of VDD and VTH for Low-Power and High-Speed Applications," Asia and South Pacific Design Automation Conference, pp.469-474, Jan. 2000 (PDF)

#2000014
T. Sakurai, "Low Power Design of Digital Circuits," International Symposium on Key Technologies for Future VLSI Systems, pp.1-5, Jan. 2000 (PDF)

#2000015
T. Sakurai, "Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control," IEEE International Symposium on Quality Electronic Design, pp.417-423, Mar. 2000 (PDF)

#2000016
T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration," IEEE Custom Integrated Circuits Conference, pp.409-412, May 2000 (PDF)

#2000017
S. Lee, and T. Sakurai, "Run-Time Voltage Hopping for Low-Power Real-Time Systems," Design Automation Conference, pp.806-809, June 2000 (PDF)

#2000018
K. Nose, S. Chae, and T. Sakurai, "Voltage Dependent Gate Capacitance and Its Impact in Estimating Power and Delay of CMOS Digital Circuits with Low Supply Voltage," International Symposium on Low Power Electronics and Design, pp.228-230, July 2000 (PDF)

#2000019
ũˆä‹MN, "Œg‘ŅŒ^’ī‚Ŧ”\î•ņ’[––ŽĀŒŧ‚ÉŒü‚Ŋ‚―’ī’áÁ”ï“d—͏WÏ‰ŧ‹Zp," ‘ÛŒÅ‘Ė‘fŽqEÞ—ŋƒRƒ“ƒtƒ@ƒŒƒ“ƒX, ƒVƒ‡[ƒgƒR[ƒX2, pp.1-25, Oct. 2000 (PDF)

#2000020
T. Sakurai, "Interconnection from Design Perspective," Advanced Metallization Conference, pp.53-58, Oct. 2000 (PDF)(PDF2)

#2000021
Y. Shin, K. Choi, and T. Sakurai, "Power Optimization of Real-Time Embedded Systems on Variable Speed Processors," International Conference on Computer Aided Design, pp.365-368, Nov. 2000 (PDF)

#2000022
T. Sakurai, "Super-connect," International Packaging Strategy Symposium, pp.19-26, Dec. 2000 (PDF)

#2000023
K. Kanda, N. D. Minh, H. Kawaguchi, and T. Sakurai, "Abnormal Leakage Suppression (ALS) Scheme for Low Standby Current SRAMs," IEEE International Solid-State Circuits Conference, pp.174-175, Feb. 2001 (PDF)

#2000024
Y. Shin, H. Kawaguchi, and T. Sakurai, "Cooperative Voltage Scaling (CVS) between OS and Applications for Low-Power Real-Time Systems," IEEE Custom Integrated Circuits Conference, pp.553-556, May 2001 (PDF)

#2000025
Y. Shin and T. Sakurai, "Coupling-Driven Bus Design for Low-Power Application-Specific Systems," Design Automation Conference, pp.750-753, June 2001 (PDF)

#2000026
Y. Shin and T. Sakurai, "Estimation of Power Distribution in VLSI Interconnects," International Symposium on Low Power Electronics and Design Accepted, Aug. 2001 (PDF)

#2000027
ũˆä‹MN, "ƒGƒŒƒNƒgƒƒjƒNƒXŽY‹Æ‚ĖŦ—ˆ‹Zp," ƒVƒ“ƒ|ƒWƒEƒ€uƒKƒ‰ƒXŽY‹Æ‹Zpí—Š2025”Nv, Mar. 2000 (PDF)

#2000028
ũˆä‹MN, "2010”N‚ĖLSI‚Æ“dŽqƒVƒXƒeƒ€," ƒGƒŒƒNƒgƒƒjƒNƒXŽĀ‘•Šwpu‰‰‘å‰ï, pp.17, Mar. 2000 (PDF)

#2000029
ũˆä‹MN, "‰ņ˜HÝŒv‚Ö‚Ė‰e‹ŋ," ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ïu‰‰—\eW, Mar. 2000 (PDF)

#2000030
ũˆä‹MN, "ƒfƒoƒCƒXƒpƒlƒ‹ƒfƒBƒXƒJƒbƒVƒ‡ƒ“," 21Ē‹I‚ð‘ņ‚­”ž“ą‘Ė‹Zpƒ[ƒNƒVƒ‡ƒbƒv, 3, pp.19-26, June 2000 (PDF)

#2000031
•―—Ņ‰ë”V, ũˆä‹MN, "’áÁ”ï“d—͏æŽZŠí‚É‚Ļ‚Ŋ‚é‰ÁŽZ‰ņ˜HŒ`ŽŪ‚ĖŒŸ“Ē," ‰ž—p•Ļ—Šw‰ï Šwpu‰‰‰ï, pp.800, Sep. 2000 (PDF)

#2000032
ó–ė—Y‘ū˜Y, ũˆä‹MN, "Adiabatic style='font-familyŠT”O‚ð‰ž—p‚ĩ‚―CMOS—pƒNƒƒbƒN‰ņ˜H," ‰ž—p•Ļ—Šw‰ï Šwpu‰‰‰ï, pp.800, Sep. 2000 (PDF)

#2000033
’Ģj, ũˆä‹MN, "‚Œø—Ķ—e—ĘŒ^‚c‚b|‚c‚bƒRƒ“ƒo[ƒ^," ‰ž—p•Ļ—Šw‰ï Šwpu‰‰‰ï, pp.801, Sep. 2000 (PDF)

#2000034
ũˆä‹MN, "LSI‚Ė•ĄŽG‰ŧ“ŪŒü," “dŽqî•ņ’ʐMŠw‰ï ƒ\ƒTƒCƒGƒeƒB‘å‰ï, pp.26, Oct. 2000 (PDF)

#2000035
’Ģj, ũˆä‹MN, "‚‘ŽŽü”g”Ø‚č‘Ö‚Ķ‰Â”\‚ČƒNƒƒbƒNķŽŒn," “dŽqî•ņ’ʐMŠw‰ï ƒ\ƒTƒGƒeƒB[‘å‰ï, pp.28, Oct. 2000 (PDF)

#2000036
•―—Ņ‰ë”V, ũˆä‹MN, "Šî”ƒoƒCƒ„ƒX§Œä‚ð‰Â”\‚É‚·‚éŽĐ“ŪÝŒvŽč–@," “dŽqî•ņ’ʐMŠw‰ï ƒ\ƒTƒGƒeƒB[‘å‰ï, pp.28, Oct. 2000 (PDF)

#2000037
ˆîŠ_ŒŦˆę, _“c_ˆę, ũˆä‹MN, "ITRSƒ[ƒhƒ}ƒbƒv€‹’•W€SPICEƒ‚ƒfƒ‹‚Ė\’z," “dŽqî•ņ’ʐMŠw‰ï ƒ\ƒTƒCƒGƒeƒB‘å‰ï, pp.28, Oct. 2000 (PDF)

#2000038
ó–ė—Y‘ū˜Y, –ėĢ_ˆę, ũˆä‹MN, "ƒfƒvƒŠ[ƒVƒ‡ƒ“Œ`CMOSƒQ[ƒg‚Ė“ÁŦ," “dŽqî•ņ’ʐMŠw‰ï ƒ\ƒTƒGƒeƒB[‘å‰ï, pp.28, Oct. 2000 (PDF)

#2000039
_“c_ˆę, ƒOƒGƒ“EƒhƒDƒbƒNEƒ~ƒ“, ėŒû”Ž, ũˆä‹MN, "’áƒXƒ^ƒ“ƒoƒC“d—Ž‚r‚q‚`‚l‚Ė‚―‚ß‚ĖˆŲíƒŠ[ƒN“d—Ž—}§•ûŽŪ," “dŽq’ʐMŠw‰ï WÏ‰ņ˜HŒĪ‹†‰ï, pp.21-25, Apr. 12, 2001 (PDF)

#2000040
T. Sakurai, "Low Power Integrated Circuit Technologies for High-Performance Extremely Low-Power Mobile Information Terminals," SSDM Short Course, Sep. 2000

#2000041
ũˆä‹MN, "ƒGƒŒƒNƒgƒƒjƒNƒX‹@ŠíÝŒv—Í‹­‰ŧ‹Zp‚Ė’ēļŒĪ‹†•ņ‘," VƒGƒlƒ‹ƒM[EŽY‹Æ‹Zp‘‡ŠJ”­‹@\, ŽÐ’c–@l“ú–{“dŽq‹@ŠBH‹Æ‰ï, Mar. 2000 (PDF)

#2000042
ũˆä‹MN, "21Ē‹I‚ĖLSI‹Zp‘ĖŒn, ’ņŒūuƒX[ƒp[ƒRƒlƒNƒgv," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX4ŒŽ1“ú†, pp.7, Apr. 2000 (PDF)

#2000043
ũˆä‹MN, "LSI‚ĖV‹Ŧ’n‚ðØ‚čŠJ‚­uƒX[ƒp[ƒRƒlƒNƒgv‹Zp," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒXEƒZƒ~ƒi[, ƒX[ƒp[ƒRƒlƒNƒgv‚ĖÕŒ‚, 1, pp.1-27, Apr. 2000 (PDF)

#2000044
ũˆä‹MN, "‚Č‚šƒVƒXƒeƒ€EƒCƒ“EƒpƒbƒP[ƒW‚ЁH\ƒVƒXƒeƒ€LSI‚Æ‚Ė‘Δä," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒXEƒZƒ~ƒi[ uƒVƒXƒeƒ€EƒCƒ“EƒpƒbƒP[ƒWv‚ĖŽĀ‘œ‚É’§‚Þ, 1, pp.1-33, Apr. 2000 (PDF)

#2000045
ũˆä‹MN, "‹‘å”zü‚ÅLSI‚ĖŒĀŠE‚ð‘Å”j," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX6ŒŽ1“ú†, pp.72-75, June 2000 (PDF)

#2000046
ũˆä‹MN, "ÝŒv‚Đ‚į‚Ý‚―’áÁ”ï“d—́E‚‘Ž‰ŧ‹Zp," ƒZƒ~ƒRƒ“ŠÖž2000, ULSI‹ZpƒZƒ~ƒi[, 3, pp.25-41, June 2000 (PDF)

#2000047
ũˆä‹MN, "ƒfƒWƒ^ƒ‹VLSIÝŒv‹Zp‚ĖŠî‘b," VLSIÝŒvƒ`ƒ…[ƒgƒŠƒAƒ‹uĀ, 2, Nov. 2000 (PDF)

#2000048
ŒĒŽ”‹MŽm, ‚‹{^, –ėĢ_ˆę, ėŒû”Ž, ũˆä‹MN, •―–{r˜Y, "Boosted Gete MOS(BGMOS)‚É‚æ‚郊[ƒNƒtƒŠ[‰ņ˜H‚Ė’ņˆÄ," 2000”Nt‹G‘æ47‰ņ‰ž—p•Ļ—ŠwŠÖ˜A˜A‡u‰‰‰ï, ÂŽRŠw‰@‘åŠwi“Œ‹žj, 28p-ya-10, Mar. 2000 (PDF)

#2000049
ŒĒŽ”‹MŽm, ‚‹{^, –ėĢ_ˆę, ėŒû”Ž, ũˆä‹MN, •―–{r˜Y, "Boosted Gate MOS(BGMOS)FƒfƒoƒCƒX‚Ɖņ˜H‚Ė‹Ķ’ē‚É‚æ‚郊[ƒNƒtƒŠ[‰ņ˜H‚Ė’ņˆÄ," “dŽqî•ņ’ʐMŠw‰ï WÏ‰ņ˜HŒĪ‹†‰ï/“dŽqƒfƒoƒCƒXŒĪ‹†‰ï/ƒVƒŠƒRƒ“Þ—ŋEƒfƒoƒCƒXŒĪ‹†‰ï‡“ŊŒĪ‹†‰ï, –kŒĐH‹Æ‘åŠwi–kŠC“đj, ED2000-124/SDM2000-106/ICD2000-60, Aug. 2000 (PDF)

#2000050
ŒĒŽ”‹MŽm, ‚‹{^, –ėĢ_ˆę, ėŒû”Ž, ũˆä‹MN, •―–{r˜Y, "Boosted Gate MOS‚ÆSuper Cut-off CMOS‚É‚æ‚郊[ƒNƒtƒŠ[‰ņ˜H," 2000”NH‹G‘æ61‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ï, –kŠC“đH‹Æ‘åŠw, 6a-ZE-3, Sep. 2000 (PDF)

#2000051
ũˆä‹MN, "“dˆģƒzƒbƒsƒ“ƒO‚É‚æ‚éSH4ƒVƒXƒeƒ€“‹ÚƒVƒXƒeƒ€‚Ė’á“d—͉ŧ," “ú—§SHƒtƒH[ƒ‰ƒ€, 2000

#2000052
T. Sakurai, "VLSI design challenges in the forthcoming decade," In-Chip Systems, Feb. 2001

#2000053
T. Sakurai, "Software and Hardware Schemes for Achieving Low-Power," Microprocessor Design Symposium, Feb. 8, 2001

#2000054
T. Sakurai, "‚‘Ž’áÁ”ï“d—͉ŧ‹Zp," ƒ[ƒ€, 2000

#2000055
ũˆä‹MN, "î•ņƒlƒbƒgƒ[ƒN‰Æ“dŒü‚ŊƒVƒXƒeƒ€‚k‚r‚h‚ðˆÓŽŊ‚ĩ‚―’áÁ”ï“d—Í‹Zp‚Ėƒ[ƒhƒ}ƒbƒv, –]‚Ü‚ę‚éƒVƒXƒeƒ€‘œ," EIAJ, Oct. 2000

#2000056
T. Sakurai, "VLSI design challenges in the forthcoming decade - What may hinder design closure -," Design closure forum, Feb. 1, 2001

#2000057
ũˆä‹MN, "ĄŒã‚ĖVLSI‚ĖÝŒv‰Û‘č‚Ɖð–@ 2010”N‚ĖLSI‰ņ˜HÝŒv‚Ė“W–]‚Æ‹Zp“I–â‘č‚Ė‰ðŒˆ," Sony Re-generation 21 Advanced Course, 2000

#2000058
ũˆä‹MN, "GSI”zü‚ĖÝŒv‰Û‘č‚Æ‰ðŒˆô‚Ė–͍õ," “dŽqî•ņ’ʐMŠw‰ï2000”Nƒ\ƒTƒCƒGƒeƒB‘å‰ï, –žŒÃ‰Ūƒr[ƒ‹‰€u_—{‰€v, TA-1, pp.27, Sep. 30, 2000

1999

#1999001
ũˆä‹MN, "21Ē‹I‚ĖLSI|‰―‚Š—~‚ĩ‚Ē, ‰―‚ðė‚é," Breakthrough, pp.4-6, Jan. 1999 (PDF)

#1999002
K. Nose and T. Sakurai, "Micro IDDQ Test using Lorenz Force MOSFET's," Symposium on VLSI circuits, pp.169-170, June 1999 (PDF)

#1999003
T. Sakurai, "Custom Circuit Techniques For High Performance And Low-Power Applications," IEEE Custom Integrated Circuits Conference, pp.277, May 1999

#1999004
ũˆä‹MN, "(ĩ‘Ō˜_•ķ)ƒVƒXƒeƒ€LSIÝŒv‚ĖŒŧó‚Ɖۑč," DAƒVƒ“ƒ|ƒWƒEƒ€'99˜_•ķW, pp.1-8, July 1999 (PDF)

#1999005
ũˆä‹MN, "ƒVƒXƒeƒ€LSI‚Í”ž“ą‘ĖŽY‹Æ‚Ė‹~ĒŽå‚É‚Č‚č‚Ī‚é‚Ė‚ЁI," ‘æ2‰ņLSIƒtƒH[ƒ‰ƒ€ ƒVƒXƒeƒ€LSI ‚Í”ž“ą‘ĖŽY‹Æ‚Ė‹~ĒŽå‚É‚Č‚č‚Ī‚é‚Ė‚ЁI, pp.1-8, May 1999

#1999006
ũˆä‹MN, "CMOS VLSI‚ĖŠî‘b‰ņ˜H‚ƐŦ”\," ‘æ1‰ņ”ž“ą‘ĖƒvƒƒZƒX‹ZpŽŌ‚Ė‚―‚ß‚ĖƒfƒoƒCƒXŠî‘buĀ[‘O•Ō], pp.3-35, Apr. 1999

#1999007
ũˆä‹MN, "”ž“ą‘Ė, ‚Į‚ą‚܂Ői‰ŧ," “ú–{ŒoÏV•·, Oct. 27, 1999 (PDF)

#1999008
T. Sakurai, "Panel on Hardware is King, Software is Queen: Has Hardware become a Second-Class Citizen to Software?," IEEE International Solid-State Circuits Conference, Panel discussion, pp.294-295, Feb. 1999

#1999009
T. Sakurai, "LSI design toward 2010 low-power technology," International Conference on VLSI and CAD, pp.325-334, Oct. 1999 (PDF)

#1999010
T. Sakurai, "Toward LSI's in the Year-From the Design Viewpoint," Symposium on Semiconductors and Integrated Circuits Technology, pp.95-105, June 1999

#1999011
T. Sakurai, "Low Voltage, High-speed VLSI Design," International Conference on Solid State Devices and Materials, pp.3-30, Sep. 1999

#1999012
ũˆä‹MN, "’ʐMEƒlƒbƒgƒ[ƒNŽž‘ã‚ĖƒVƒXƒeƒ€LSI‹Zp‚Ė“W–]," ‘æ3‰ņƒVƒXƒeƒ€LSIƒtƒH[ƒ‰ƒ€ ’ʐMEƒlƒbƒgƒ[ƒNŽž‘ã‚ĖƒVƒXƒeƒ€LSI‹Zp, pp.1-15, Sep. 1999

#1999013
ũˆä‹MN, "ƒVƒXƒeƒ€LSIu‚‹@”\‚Æ’á“d—́vŽĀŒŧ," “ú–{ŒoÏV•·, May 1999 (PDF)

#1999014
ũˆä‹MN, "‚WÏƒVƒXƒeƒ€LSI‚Ė“ŪŒü‚ƏÁ”ï“d—͉ŧ‘Ήž‹Zp," STARC symposium 99, pp.5-12, Sep. 1999 (PDF)

#1999015
T. Sakurai, "Toward LSI's in the year 2010," IC Design Education Center (IDEC) in Korea Conference, Kwangju, Korea, pp.3-69, Oct. 1999

#1999016
ũˆä‹MN, "(ĩ‘Ō˜_•ķ)2010”N‚ĖLSI‚ƏÁ”ï“d—Í‹Zp," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ‘, pp.65-72, July 1999

#1999017
ũˆä‹MN, "î•ņˆ—‚ð’S‚ĪCMOS LSI‚Ė˜b," î•ņˆ—, pp.184-187, Feb. 1999 (PDF)

#1999018
ũˆä‹MN, "‘æ8‰ņ“dŽq‰ņ˜HĒŠE‘å‰ï ‘å‰ïŠî’ēu‰‰ 2010”N‚ĖLSI‚Æ“dŽqƒVƒXƒeƒ€`LSI‚Đ‚į‚ĖƒƒbƒZ[ƒW`," JPCA NEWS, pp.3-15, Oct. 1999 (PDF)

#1999019
ũˆä‹MN, "‚WÏ‰ŧ‚ƍŽÚ‹Zp‚ðŠî”Õ‚Æ‚·‚éƒVƒXƒeƒ€LSI," “úŒoƒGƒŒƒNƒgƒƒjƒNƒX, pp.120-134, Mar. 1999 (PDF)

#1999020
ũˆä‹MN, "ÝŒv‚ĖŽ‹“_‚Đ‚įŒĐ‚―SOI‹Zp," JST Forum, Mar. 16, 1999

#1999021
ũˆä‹MN, "Œƒ“Ū‚·‚éLSIŽY‹Æ," ŽO•H“d‹@‹Z•ņ, 74, 3, Mar. 25, 2000 (PDF)

#1999022
ũˆä‹MN, "[‘ā] ‰æ‘œEƒOƒ‰ƒtƒBƒbƒNƒX‚ĖÅV‚Ė“Ū‚Ŧ," ‘æ4‰ņLSIƒtƒH[ƒ‰ƒ€ ‰æ‘œEƒOƒ‰ƒtƒBƒbƒNƒX‚ƃVƒXƒeƒ€LSI‹Zp, pp.1-1-1-8, Nov. 26, 1999

#1999023
T. Sakurai, "Challenges in VLSI Design Toward the New Millennium," IC Design Education Center (IDEC) in Korea Conference, Oct. 1999 (PDF)

#1999024
ũˆä‹MN, "‘å‹K–ÍLSI ŒĖáŒÂŠŠČ’P‚ɐf’f," “úŠ§H‹ÆV•·, June 18, 1999 (PDF)

#1999025
ũˆä‹MN, "ŠeŽÐ, “ūˆÓ•Š–ė‚ɃŠƒ\[ƒX‚ðW’†," “ú–{ŒoÏV•·, Oct. 27, 1999 (PDF)

#1999026
ũˆä‹MN, "“ú–{‚Ė”ž“ą‘Ė‹ZpŠJ”­iŽå‚ɉņ˜HÝŒv‹Zpj‚É‚Ļ‚Ŋ‚é‚ą‚ę‚܂łƍĄŒã‚Ė‰Û‘č," “ú–{­ô“ŠŽ‘‹âs, ƒCƒmƒx[ƒVƒ‡ƒ“ŒĪ‹†‰ï, Feb. 2000

#1999027
ũˆä‹MN, "2010”N‚ĖLSI‰ņ˜HÝŒv‚Ė“W–]‚Æ‹Zp“I–â‘č‚Ė‰ðŒˆ," Sony Re-generation 21 Advanced Course ŒĪC, Dec. 1999

#1999028
ũˆä‹MN, "ƒVƒXƒeƒ€‚k‚r‚h‹Zp‹y‚Ņ‚‘Ž’áÁ”ï“d—͉ŧ‹Zp‚ɂ‚Ē‚Ä," ž‰š“dŠíŽY‹Æ(Š”), Sep. 1999

#1999029
ũˆä‹MN, "‰ņ˜HÝŒv‚Ö‚Ė‰e‹ŋ," ‰ž—p•Ļ—Šw‰ï, Mar. 2000

#1999030
ũˆä‹MN, "2010”N‚Ė‚k‚r‚h‚Æ“dŽqƒVƒXƒeƒ€ `‚k‚r‚h‚Đ‚į‚ĖƒƒbƒZ[ƒW`Electronic Systems and LSIfs in Year 2010 -A Message from LSIfs -," ŽĀ‘•Šw‰ï, Mar. 2000

#1999031
ũˆä‹MN, "2010”N‚Ė‚k‚r‚h‚Æ“dŽqƒVƒXƒeƒ€`‚k‚r‚h‚Đ‚į‚ĖƒƒbƒZ[ƒW`," ‘æ‚W‰ņ“dŽq‰ņ˜HĒŠE‘å‰ï ‘å‰ïŠî’ēu‰‰, 1999

#1999032
ũˆä‹MN, "2010”N‚ĖLSI‚Æ’áÁ”ï“d—Í‹Zp," •xŽm’ĘCADŠÖŒWŽ‰Ę”­•\‰ï, Nov. 2000

#1999033
T. Sakurai, "Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's," IEEE Custom Integrated Circuits Conference, May 1999

#1999034
N. Minh Duc, T. Sakurai, "ƒRƒ“ƒpƒNƒg‚ȍ‚‘Ž’áÁ”ï“d—̓‰ƒCƒuƒ‰ƒŠ[‚ĖŒĪ‹†," CŽm˜_•ķ, “Œ‹ž‘åŠw, 2000 (PDF)

#1999035
T. Sakurai, "Achieving Low-Power Through VDD and VTH Control," Intel, Mar. 2000

#1999036
_“c_ˆę, ũˆä‹MN, "’á“dˆģ‚Ŧ”\ƒNƒƒbƒNƒWƒFƒlƒŒ[ƒ^‚ÉŠÖ‚·‚éŒĪ‹†," CŽm˜_•ķ, “Œ‹ž‘åŠw, Feb. 2000 (PDF)

1998

#1998001
ũˆä‹MN, ėŒû”Ž, ‚į, "’áÁ”ï“d—Í, ‚‘ŽLSI‹Zpiũˆä‹MNE•Ōj," ƒŠƒAƒ‰ƒCƒYŽÐ, “Œ‹ž, 4-89808-004-9, pp.3-15, 148-152, Feb. 1998

#1998002
T. Sakurai, "Challenges for Low-Power and High-performance Chips," IEEE Design & Test of Computers, Vol., No.3, pp.119-124, Sep. 1998 (PDF)

#1998003
S. Ishiwata and T. Sakurai, "Future Directions of Media processors," IEICE Transactions on Electronics, Vol.E81-C, No.5, pp.629-635, May 1998 (PDF)

#1998004
H. Kawaguchi and T. Sakurai, "A Reduced Clock-Swing Flip-Flop(RCSFF)for 63% Power Reduction," IEEE Journal of Solid-State Circuits, Vol.33, No.5, pp.807-811, May 1998 (PDF)

#1998005
ũˆä‹MN, "ƒVƒXƒeƒ€LSI‚ĖƒAƒvƒŠƒP[ƒVƒ‡ƒ“‚ƃVƒXƒeƒ€LSI‚Ė‰Û‘č," “d‹Cî•ņ’ʐMŠw‰ïŽ, pp.1082-1086, Nov. 1998 (PDF)

#1998006
H. Kawaguchi, K. Nose, and T. Sakurai, "A COMS Scheme for 0.5v Supply Voltage with Pico-Ampere Standby Current," IEEE International Solid-State Circuits Conference, 12.4, pp.192-193, Feb. 1998 (PDF)

#1998007
H. Kawaguchi and T. Sakurai, "Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines," Asia and South Pacific Design Automation Conference, pp.35-43, Feb. 1998 (PDF)

#1998008
T. Sakurai, "Panel on How Will Media processors the Next Decade?," IEEE International Solid-State Circuits Conference, Panel discussion, pp.264-265, Feb. 1998

#1998009
T. Sakurai, "Audio and Video Digital Processing," IEEE Custom Integrated Circuits Conference, pp.167, May 1998

#1998010
H. Kawaguchi, Y. Itaka and T, Sakurai, "Dynamic Leakage Cut-off Scheme Low-Voltage SRAM's," Symposium on VLSI Circuits, pp.140-141, June 1998 (PDF)

#1998011
R. Allmon and T. Sakurai, "Panel on Visions of Computers in the year 2005," Symposium on VLSI Circuits, pp.69, June 1998 (PDF)

#1998012
H. Kawaguchi, K. Nose, and T. Sakurai, "A COMS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current," International Workshop on Advanced LSIs, pp.45-49, July 1998 (PDF)

#1998013
S. Takeuchi and T. Sakurai, "A-Fine Grain, Current Mode Scheme for VLSI Proximity Search Engine," International Conference on Computer Design, pp.184-185, Oct. 1998 (PDF)

#1998014
K. Nose and T. Sakurai, "Integrated Current Sensing Device for Micro IDDQ Test," Asian Test Symposium, pp.323-326, Dec. 1998 (PDF)

#1998015
ũˆä‹MN, "VLSI‚ð–ÚŽw‚ĩ‚Ä," ŒÅ‘ĖƒGƒŒƒNƒgƒƒjƒNƒXEƒIƒvƒgƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†”­•\‰ï, pp.63-72, Feb. 1998

#1998016
’|“ā―“ņ, ũˆä‹MN, "‚–§“x_Œo‰ņ˜H–Ô‚ĖÝŒv," ‘æ45‰ņ‰ž—p•Ļ—Šw‰ïŠÖŒW˜A‡u‰‰‰ï, pp. 890, Mar. 1998

#1998017
ũˆä‹MN, "Á”ï“d—Í," ”zü’x‰„‚Đ‚įŒĐ‚―LSI‚ĖWÏ‰ŧŒĀŠE ‰ž—p•Ļ—Šw‰ïƒVƒŠƒRƒ“ƒeƒNƒmƒƒW[ŒĪ‹†‰ï, pp.28-33, May 1998 (PDF)

#1998018
ėŒû ”Ž, ˆä‚N“ņ, ũˆä‹MN, "’á“dˆģSRAM‚Ė‚―‚ß‚ĖDynamic Leakage Cut-offÝŒv–@," “dŽqî•ņ’ʐMŠw‰ï‹ZpŒĪ‹†•ņ, 98, 119, pp.1-4, June 1998 (PDF)

#1998019
ˆä‚N“ņ, ũˆä‹MN, "”zü’x‰„‹ßŽ—ļ“x‚Ėƒ‚[ƒƒ“ƒgƒ}ƒbƒ`ƒ“ƒOŽŸ”ˆË‘ķŦ," 59‰ņ‰ž—p•Ļ—Šw‰ïŠwpu‰‰‰ï, pp.781, Sep. 1998

#1998020
ˆä‚N“ņ, ũˆä‹MN, "ƒfƒB[ƒvƒTƒuƒ~ƒNƒƒ“”zü‚ĖƒŠƒs[ƒ^[‘}“üÅ“K‰ŧ," “dŽqî•ņ’ʐMŠw‰ïƒ\ƒTƒCƒGƒeƒB‘å‰ï, pp.93, Sep. 1998 (PDF)

#1998021
ėŒû ”Ž, –ėĢ _ˆę, ũˆä‹MN, "A COMS Scheme for 0.5v Supply Voltage with Pico-Ampere Standby Current," “dŽqŠw‰ï‹É”ũ\‘ĒWÏƒfƒoƒCƒX’ēļę–åˆÏˆõ‰ï, Mar. 1998

#1998022
ũˆä‹MN, •“c’‰L, "CMOS LSI‹Zp," ‚h‚h‚rŽY‹Æ‰ČŠwƒVƒXƒeƒ€ƒY, pp.1-33, Jan. 1998

#1998023
ũˆä‹MN, "2010”N‚ĖVLSI‚ð–ÚŽw‚ĩ‚Ä," “Œ‹ž‘åŠw ŒÅ‘ĖƒGƒŒƒNƒgƒƒjƒNƒXEƒIƒvƒgƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†”­•\‰ï, pp.63-72, 1998 (PDF)

#1998024
ũˆä‹MN, "ƒƒfƒBƒAƒvƒƒZƒbƒT‚ÍŽŸ‚Ė10”N‚ð‚Į‚ĪŽx”z‚·‚é‚Đ," ƒGƒŒƒNƒgƒƒjƒNƒX, pp.4-6, Apr. 1998

#1998025
ũˆä‹MN, "ƒVƒXƒeƒ€LSI‚ĖĄŒã‚Ė“W–]‚Ɖۑč," CMP‹Zp‚ĖŠî‘b‚ÆŽĀ—áuĀƒVƒŠ[ƒY‘æ3‰ņ, pp.1-1-1-6, 1998

#1998026
ũˆä‹MN, "”ž“ą‘Ė, 2‚‚Ė’§í ’áÁ”ï“d—͉ŧ‚ƃVƒXƒeƒ€LSI‰ŧ," “ú–{ŒoÏV•·, May 18, 1998 (PDF)

#1998027
ũˆä‹MN, "ULSIƒvƒƒZƒX‚É‚Ļ‚Ŋ‚é“š”zü‹Zp‚Ė“ŪŒü‚Æ“W–]," CMP‹Zp‚ĖŠî‘b‚ÆŽĀ—áuĀƒVƒŠ[ƒY‘æ3‰ņ, pp.2-1-2-6, Sep. 1998

#1998028
ũˆä‹MN, "’áÁ”ï“d—͍‚‘ŽLSI‚ĖĄŒã‚ð’T‚é," ƒŠƒAƒ‰ƒCƒYÅV‹ZpuĀ, pp.1-1-1-4, Oct. 1998

#1998029
ũˆä‹MN, "ƒVƒXƒeƒ€LSI‚ĖŒŧó‚Æ–Ē—ˆ," DAFS‹Zp‹ģˆįƒZƒ~ƒi[, pp.23-57, Oct. 1998

#1998030
T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama, "Variable supply-voltage scheme for low-power high-speed CMOS digital design," IEEE Journal of Solid-State Circuits, Vol.33, No.3, pp.454-462, Mar. 1998 (PDF)

#1998031
W. Bidermann and T. Sakurai, "Foreword," IEEE Journal of Solid-State Circuits, Vol.33, No.5, pp.674-675, May 1998 (PDF)

#1998032
ũˆä‹MN, "”ž“ą‘ĖWÏ‰ņ˜HiVLSIj‚Ė’§í," ķŽYŒĪ‹†, 50, 10, pp.28-34, Oct. 1998 (PDF)

#1998033
K. Nose and T. Sakurai, "Closed-Form Expressions for Short-Circuit Power Short-Channel CMOS Gates and Its Scaling Characteristics," International Technical Conference on Circuits/Systems, Computers and Communications, pp.1741-1744, July 1998 (PDF)

#1998034
ˆä‚Nm, ũˆä‹MN, "”ũŨ‰ŧ‚ģ‚ę‚―LSI‚É‚Ļ‚Ŋ‚éƒcƒŠ[\‘Ē”zü‚Ö‚ĖÅ“KƒŠƒs[ƒ^‘}“ü," CŽm˜_•ķ, “Œ‹ž‘åŠw, Feb. 1999 (PDF)

#1998035
–ėĢ_ˆę, ũˆä‹MN, "’áÁ”ï“d—ÍCMOS LSIŽĀŒŧ‚ÉŒü‚Ŋ‚―Á”ï“d—Í‚Ė‰ðÍ“IÅ“K‰ŧŽč–@‚ƃ}ƒCƒNƒIDDQƒeƒXƒg," CŽm˜_•ķ, “Œ‹ž‘åŠw, 1999

#1998036
ũˆä‹MN, "‚Ŧ”\E’áÁ”ï“d—Í‚ĖULSI‚É‚Ļ‚Ŋ‚éCMP‚Ö‚ĖŠú‘Ō," , 1998

#1998037
ũˆä‹MN, "ÝŒv‚ĖŽ‹“_‚Đ‚įŒĐ‚―‚r‚n‚h‹Zp," JST Forum, 1999

#1998038
T. Sakurai, "Challenges in VLSI Design ower and Interconnection," TI Symposium, 1998

#1998039
ũˆä‹MN, "CMOS LSI‚Ė‚Ļ˜b," î•ņˆ—, 1998

#1998040
T. Sakurai, "Moore's Law : when to break?," IEEE Symposia on VLSI Technology and Circuits, 1998

#1998041
T. Sakurai, "LSIfs toward the Year 2010," Tutorial, Sendai, 1998

1997

#1997001
ėŒû ”Ž, "LSI‚Ė’áÁ”ï“d—͉ŧ," “Œ‹ž‘åŠwķŽY‹ZpŒĪ‹†Š‘æ6‰ņ‹Zp”­•\‰ï ‹ZpŠŊ“™‚É‚æ‚é‹Zp•ņ‘, 1997 (PDF)

#1997002
ũˆä‹MN, "2010”N‚ĖVLSI‚ÉŒü‚Ŋ‚Ä‚ĖÝŒv," DA Show, 1997

#1997003
ũˆä‹MN, "CMOS LSI‚Ė‹Zp“ŪŒüĒ‚WÏ‰ŧ‚ÉŒü‚Ŋ‚―‰Û‘čv," , 1997

#1997004
•“c’‰L, ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒACMOSVLSI‚Ė‚―‚ß‚Ė’áÁ”ï“d—͉ņ˜HÝŒv‹Zpiĩ‘Ō˜_•ķj," “dŽqî•ņ’ʐMŠw‰ïŽ, May 1997 (PDF)

#1997005
I. A. Young and T. Sakurai, "Editorial," IEEE Journal of Solid-State Circuits, Vol.32, No.5, pp.618-620, May 1997 (PDF)

#1997006
ũˆä‹MN, "2010”N‚ĖVLSI‚ð–ÚŽw‚ĩ‚Ä," ŒÅ‘ĖƒGƒŒƒNƒgƒƒjƒNƒXEƒIƒvƒgƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†”­•\‰ï, “Œ‹ž‘åŠw, pp.63-72, Feb. 1998

#1997007
T. Kuroda and T. Sakurai, "Low-Power Circuit Design (invited)," Asia and South Pacific Design Automation Conference, 1, Jan. 1997

#1997008
T. Sakurai , T. Kuroda, "Low-Power Circuit Design for Multimedia LSI's (invited)," European Design and Test Conference, Mar. 1997

#1997009
K. Okada and T. Sakurai, "Audio and Video DSPs," IEEE Custom Integrated Circuits Conference, pp.223, May 1997

#1997010
T. Sakurai and T. Kuroda, "Low Voltage Technology and Circuits (invited)," Mead Microelectronics Conference, Lausanne, Switzerland, June 1997

#1997011
H. Kawaguchi and T. Sakurai, "A Reduced Clock-Swing Flip-Flop( RCSFF ) for 63% Clock Power Reduction," Symposium on VLSI Circuits, pp.97-98, June 1997 (PDF)

#1997012
T. Sakurai, H. Kawaguchi, and T. Kuroda, "Low-Power CMOS Design through VTH Control and Low-Swing Circuits (invited)," Digest International Symposiumon Low-Power Electronics and Design, pp.1-6, Sep. 1997 (PDF)

#1997013
H. Kawaguchi and T. Sakurai, "Noise Expressions for Capacitance-Coupled Distributed RC Lines," ACM / IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.270-279, Dec. 1997 (PDF)

#1997014
H. Kawaguchi and T. Sakurai, "Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines," Asia and South Pacific Design Automation Conference, pp.35-43, Feb. 1998

#1997015
ũˆä‹MN, "ƒVƒXƒeƒ€LSI‚Ė–Ē—ˆ‚Æ”ž“ą‘Ė‚ĖŒĀŠE," “ú–{ŒoÏV•·, Oct. 28, 1997 (PDF)

#1997016
ėŒû ”Ž, ũˆä‹MN, "Serially Insertion of Cut-off MOSFET CMOS ( SCCMOS )‚É‚æ‚é’áÁ”ï“d—͉ŧ," •―Ž9”Nt‹G‘æ44‰ņ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ïu‰‰—\eW, pp.744, Mar. 1997 (PDF)

#1997017
ũˆä‹MN, "LSI”zü‚ÉŠÖ‚·‚é‰Û‘č‚Æ‰ðŒˆô‚ÖŒü‚Ŋ‚Ä‚Ė“W–]," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï0.01um LSI‚ÉŒü‚Ŋ‚―ƒVƒ“ƒ|ƒWƒEƒ€, pp.52-65, May 1997

#1997018
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Æ’áÁ”ï“d—͐݌v‹Zp," ‰ž—p•Ļ—Šw‰ïƒXƒN[ƒ‹SiƒfƒoƒCƒX‚ĖV‹@Žē, pp.73-91, Oct. 1997

#1997019
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Æ’áÁ”ï“d—͐݌v," ’īWÏ‰ŧƒfƒoƒCƒXEƒVƒXƒeƒ€‘æ165ˆÏˆõ‰ï‘æ4‰ņŒĪ‹†‰ïŽ‘—ŋ, pp.17-24, Oct. 1997

#1997020
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒAVLSI‰æ‘œiƒƒfƒBƒAƒvƒƒZƒbƒTj," “dŽqî•ņ’ʐMŠw‰ïEķŠU‹ģˆįuĀ, Oct. 1997

#1997021
’|“ā―“ņ, ũˆä‹MN, "‚–§“xVLSI_Œo‰ņ˜H–Ô‚ĖÝŒv," ‰ž—p•Ļ—ŠwŠÖŒW˜A‡u‰‰‰ï, Mar. 1998

#1997022
H. Kawaguchi, K. Nose, and T. Sakurai, "A CMOS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current," “d‹CŠw‰ïE‹É”ũ\‘ĒWÏƒfƒoƒCƒX’ēļę–åˆÏˆõ‰ï, Mar. 1998

#1997023
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Æ’áÁ”ï“d—͐݌v‹Zp," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ïEŽY‹Æ‹Zp§’k‰ï, Jan. 1997

#1997024
ũˆä‹MN, "ÝŒv—Í‚Ė‰Û‘č," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï, DA-WG, Feb. 1997

#1997025
ũˆä‹MN, "‚ą‚ę‚Đ‚į‚Ė’á“dˆģE’áÁ”ï“d—̓fƒoƒCƒX‚ðl‚Ķ‚é," Breakthrough, Mar. 1997

#1997026
ũˆä‹MN, "ƒVƒXƒeƒ€LSIÝŒvŠT˜_," Design Automation show Šî’ēu‰‰, B1, July 1997

#1997026
ũˆä‹MN, •“c’‰L, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Ė‚―‚ß‚Ė’áÁ”ï“d—͉ņ˜HÝŒv‹Zp," ISSŽY‹Æ‰ČŠwƒVƒXƒeƒ€ƒY, Apr. 1997

#1997027
ũˆä‹MN, "CMOS LSI‚ð—‰ð‚·‚é," Triceps, pp.1-114, Aug. 1997

#1997027
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Æ’áÁ”ï“d—͐݌v‹Zp," ƒVƒŠƒRƒ“ƒiƒmƒGƒŒƒNƒgƒƒjƒNƒXŒĪ‹†‰ï, pp.1-46, June 1997

#1997028
ũˆä‹MN, "’á“dˆģ‰ŧ‚Ė‹Zp‚ĖƒgƒŒƒ“ƒh," “ú–{H‹Æ‹ZpƒZƒ“ƒ^[, pp.1-37, Sep. 1997

#1997029
ũˆä‹MN, "LSI‚Ė’áÁ”ï“d—͉ŧE‚‘Ž‰ŧ‹Zp‚Æ‚ŧ‚ĖŽĀÛ—á," “ú–{ƒeƒNƒmƒZƒ“ƒ^[, pp.1-44, Dec. 1997

#1997030
ũˆä‹MN, •“c’‰L, "’á“d—ÍCMOS LSI‹Zp," ISSŽY‹Æ‰ČŠwƒVƒXƒeƒ€ƒY, pp.1-33, Jan. 1998

#1997031
ũˆä‹MN, "Œy‚ĒU“Ū‚Å“Ū‚­LSI," “ú–{ŒoÏV•·, June 14, 1997 (PDF)

#1997032
ũˆä‹MN, "Á”ï“d—Í13-30%’áŒļ," “ú–{ŽY‹ÆV•·, July 22, 1997 (PDF)

#1997033
ũˆä‹MN, "•ÏŠv”—‚į‚ę‚锞“ą‘ĖŽY‹Æ," “ú–{ŽY‹ÆV•·, Aug. 18, 1997 (PDF)

#1997034
ũˆä‹MN, "ƒVƒXƒeƒ€LSI‚ŐV‚―‚Č•t‰Á‰ŋ’l‘n‘Ē," “ú–{ŽY‹ÆV•·, Aug. 18, 1997 (PDF)

#1997035
ũˆä‹MN, "ƒuƒŒ[ƒNƒXƒ‹[‚ð–͍õ," “ú–{ŽY‹ÆV•·, Aug. 19, 1997 (PDF)

#1997036
ũˆä‹MN, "ƒrƒWƒlƒX‚Æ‹Zp‚Ė—ž—§‚ð‚ß‚ī‚ĩ," “ú–{ŽY‹ÆV•·, Aug. 19, 1997 (PDF)

#1997037
ũˆä‹MN, "‰ņ˜HÝŒv‚ŏÁ”ï“d—Í‚ð‘啝íŒļ," ”ž“ą‘ĖŽY‹ÆV•·, Aug. 27, 1997 (PDF)

1996

#1996001
H. Hara, M. Matsui, G. Otomo, K. Seta, and T. Sakurai, "Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment," IEICE Transactions on Electronics, Vol.E79-C, No.6, pp.750-756, June 1996 (PDF)

#1996002
A. Parameswar, H. Hara, and T. Sakurai, "A Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications," IEEE Journal of Solid-State Circuits, Vol.31, No.6, pp.804-809, June 1996 (PDF)

#1996003
T. Kuroda and T. Sakurai, "Threshold-Voltage Control Schemes through Substrate-Bias for Low-Power High-Speed CMOS LSI Designs (invited)," Journal of VLSI Signal Processors, Vol.13, No.2/3, pp.191-201, Aug. 1996

#1996004
T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9-V, 150-MHz 10-mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE Journal of Solid-State Circuits, Vol.31, No.11, pp.1770-1779, Nov. 1996 (PDF)

#1996005
T. Kuroda, T. Fujuta, T. Nagamatsu, S. Yoshioka, T. Sei, K. Matsumoto, Y. Hamura, T. Mori, M. Murota, M. Kakumu, and T. Sakurai, "A High-Speed Low-Power 0.3um CMOS Gate Array with Variable Threshold Voltage (VT) Scheme," IEEE Custom Integrated Circuits Conference, pp.53-56, May 1996

#1996006
T. Sakurai, "Video, Image and Speech Digital Signal Processing," IEEE Custom Integrated Circuits Conference, pp.349, May 1996

#1996007
K. Suzuki, T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kato, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage (VT) Scheme," 4th International Workshop on Advanced LSI's, pp.150-158, July 1996

#1996008
T. Sakurai and T. Kuroda, "Achieving Low-Power Through Control of Threshold Voltage (invited)," XXXVth General Assembly of the International Union of Radio Science (URSI) Abstracts, pp.168, Aug. 1996

#1996009
T. Kuroda, T. Fujita, S. Mita, T. Mori, K. Matsuo, M. Kakumu, and T. Sakurai, "Substrate Noise Influence on Circuit Performance in Variable Threshold-Voltage Scheme," International Symposium on Low Power Electronics and Design, pp.309-312, Oct. 1996 (PDF)

#1996010
T. Sakurai and T. Kuroda, "Tutorial on Low-Power Design Methodology (invited)," Proc. of the Synthesis and System Integration of Mixed Technologies (SASIMI), pp.3-10, Nov. 1996

#1996011
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Æ’áÁ”ï“d—͐݌v‹Zp," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï ę‹Æ‹Zp§’k‰ï, Jan. 1997

#1996012
T. Sakurai and T. Kuroda, "Low-Power Circuit Design for Multimedia LSI's," European Design and Test Conference, Mar. 1997

#1996013
T. Sakurai and T. Kuroda, "Low-Voltage Technology and Circuits (invited)," Mead Microelectronics Conference, Mar. 1997

#1996014
ũˆä‹MN, "ÝŒv—Í‚Ė‰Û‘č," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï DA-WG, Feb. 1997

#1996015
T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kobayashi, T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kobayashi, T. Higashi, M. Klein, J. Thomson, R. Carpenter, R. Donthi, D. Renfrow, J. Zheng, L. Tinkey, B. Maness, J. Battle, S. Purcell, and T. Sakurai, "350MHz Time-Multiplexed 8-Port SRAM and Word-Size Variable Multiplier for Multimedia DSP," IEEE International Solid-State Circuits Conference, 9.4, pp.150-151, Feb. 1996 (PDF)

#1996016
Y. Unekawa, K. Fkuda, K. Sakue, T. Nakao, S. Yoshioka, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motomiya, Y. Ohba, K. Ise, M. Ono, K. Fujiwara, Y. Miyazawa, T. Kuroda, Y. Kamitani, T. Sakurai, and A. Kanuma, "A 5Gb/s 8 x 8 ATM Switch Element CMOS LSI Supp. Rting Five Quality-Of-Service Classes with 200MHz LVDS Interface," IEEE International Solid-State Circuits Conference, 7.3, pp.118-119, Feb. 1996 (PDF)

#1996017
T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. yoshioka, F. Sano, M. Norishima, M. Murota, M. Kato, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme," IEEE International Solid-State Circuits Conference, 10.3, pp.166-167, Feb. 1996 (PDF)

#1996018
K. Seki, Y. Unekawa, K. Sakue, T. Nakano, S. Yoshida, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motoyama, Y. Ohba, K. Ise, M. Ono, K. Fujikawara, Y. Miyazawa, T. Kuroda, Y. Kamatani, T. Sakurai, and A. Kanuma, "A 5Gb/s ATM Switch Element CMOS LSI Supporting 5 Quality-of-Service Classes with 200MHz LVDS Interface," Technical Report of IEICE, ED96-51, pp.57-64, June 1996

#1996019
“Ą“c“N–į, •“c’‰O, ŽO“c^“ņ, ‰iž “O, ‹g‰ŠWˆę, ē–ė•ķ•F, –@“‡­”V, Žš“c‰ë”V, ‰ÁŒÃ^‹Õ, ˆßėģ–ū, Še–ąģˆę, ũˆä‹MN, "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Professor with Variable-Threshold-Voltage(VT) Scheme," “dŽqî•ņ’ʐMŠw‰ï WÏ‰ņ˜HŒĪ‹†‰ï MŠw‹Z–@, ED96-49/SDM96-32/ICD96-52, pp.43-48, June 1996

#1996020
ũˆä‹MN, •“c’‰O, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Æ’áÁ”ï“d—͐݌v‹Zpiĩ‘Ōj," “d‹CŠw‰ï ‘æ43‰ņ”ž“ą‘Ėę–åuĀ, pp.1-32, July 1996

#1996021
ũˆä‹MN, "uƒ}ƒ‹ƒ`ƒƒfƒBƒAVLSI‰æ‘œviƒƒfƒBƒAƒvƒƒZƒbƒTj," “dŽqî•ņ’ʐMŠw‰ï ķŠU‹ģˆįuĀ, Oct. 1996

#1996022
ũˆä‹MN, "ƒƒfƒBƒAƒvƒƒZƒbƒT," “dŽqî•ņ’ʐMŠw‰ï LSIÝŒv‹Zp‚Ė–Ē—ˆ‚ðl‚Ķ‚é”ú”iŒÎƒ[ƒNƒVƒ‡ƒbƒv, pp.85-108, Nov. 1996

#1996023
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Ė‚―‚ß‚Ė’áÁ”ï“d—͉ņ˜HÝŒv‹Zp," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï ƒ}ƒCƒNƒƒRƒ“ƒsƒ…[ƒ^[‚ÉŠÖ‚·‚é’ēļŒĪ‹†•ņ‘, 96-ƒV-1, pp.24-39, Apr. 1996

#1996024
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Ė‚―‚ß‚Ė’áÁ”ï“d—͉ņ˜HÝŒv‹Zp," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï ’īWÏæ’[ƒVƒXƒeƒ€’ēļŒĪ‹†•ņ‘‡U, 96-Šî\10, pp.48-53, Apr. 1996

#1996025
ũˆä‹MN, "LSI”sí‚ÉŠÖ‚·‚é‰Û‘č‚Æ‰ðŒˆô‚ÖŒü‚Ŋ‚Ä‚Ė“W–]," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï Åæ’[‰ÁHWG, Apr. 1996

#1996026
ũˆä‹MN, "ƒƒfƒBƒAƒvƒƒZƒbƒT‚ĖŠJ”­‚Ɖž—p," “ú–{H‹Æ‹ZpƒZƒ“ƒ^[, pp.43-65, May 1996

#1996027
ũˆä‹MN, "’áÁ”ï“d—ÍLSIŠJ”­‚Æ‚ŧ‚ĖŠÂ‹Ŧ," Electronic Journal, pp.13, Aug. 1996

#1996028
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒA‚ÆČÁ”ï“d—͐݌v‹Zp," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï, Sep. 1996

#1996029
ũˆä‹MN, •“c’‰O, "LSI‚Ė’áÁ”ï“d—͉ŧE‚‘Ž‰ŧ‹Zp," “ú–{ƒeƒNƒmƒZƒ“ƒ^[, pp.1-44, Dec. 1996

#1996030
ũˆä‹MN, "ƒ}ƒ‹ƒ`ƒƒfƒBƒALSI‚Æ’áÁ”ï“d—͐݌v‹Zp," “ú–{“dŽqH‹ÆU‹ŧ‹Ķ‰ï, Sep. 1996

1995

#1995001
K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, "50% Active Power Saving without Speed Degradation Using Standby Power Reduction (SPR) Circuit," IEEE International Solid-State Circuits Conference, 19.4, pp.318-319, Feb. 1995 (PDF)

#1995002
T. Sakurai and T. Kuroda, "Outline of Low-Power LSI Design(invited)," “dŽqî•ņ’ʐMŠw‰ï ‘‡‘å‰ï, Mar. 1995

#1995003
T. Kuroda and T. Sakurai, "Overview of Low-Power ULSI Circuit Techniques(invited)," IEICE Transactions on Electronics, Vol.E78-C, No.4, pp.334-344, Apr. 1995 (PDF)

#1995004
T. Sakurai and T. Kuroda, "Tutorial on Low-Power LSI Design(invited)," the 8th Karuizawa Workshop on Circuits and Systems, pp.209-214, Apr. 1995

#1995005
T. Kuroda and T. Sakurai, "Low-Power Circuit Design using Pass-Transistor Logic and Substrate-bias Control(invited)," the 8th Karuizawa Workshop on Circuits and Systems, pp.215-220, Apr. 1995

#1995006
G. Otomo, H. Hara, T. Oto, K. Seta, K. Kitagaki, S, Ishiwata, S. Michinaka, T. Shimazawa, M. Matsui, T. Demura, M. Koyama, Y. Watanabe, F. Sano, A. Chiba, K. Matsuda, and T. Sakurai, "Special Memories and Embedded Memories in MPEG Environments(invited)," IEEE Custom Integrated Circuits Conference, 8.1, May 1995

#1995007
T. Sakurai and T. Kuroda, "Lecture on Low-Power VLSI Design(invited)," Japan Industrial Engineering Center Seminar, July 1995

#1995008
T. Sakurai, "Tutorial on Low-Power Circuit Design Methodology(invited)," Asia and South Pacific Design Automation Conference, Aug. 1995

#1995009
A. Chiba, K. Matsuda, Y. Watanabe, G. Otomo, H. Hara, M. Matsui, and T. Sakurai, "Special Memory and Embedded Memory Macrocells in Multimedia LSI's(invited)," Technical Report of IEICE, ICD95-77, pp.51-57, Aug. 1995

#1995010
T. Sakurai, "Low-Power Circuit Design for Multimedia(invited)," Proc. of the International Conference on VLSI and CAD (ICVC), pp.37-42, Oct. 1995

#1995011
F. Sano, A. Chiba, K. Matsuda, Y. Watanabe, G. Otomo, H. Hara, M. Matsui, and T. Sakurai, "Design Methodology for Special Purpose Memories in Multimedia LSI's and its Application to MPEG2 Decoder(invited)," Technical Report of IEJ, ECT-95-61, pp.29-38, Sep. 11, 1995

#1995012
T. Sakurai and T. Kuroda, "Design Methodology for Low-Power and High-Speed VLSI Design(invited)," Japan Industrial Engineering Center Seminar, Nov. 28, 1995

#1995013
T. Kuroda and T. Sakurai, "Low-Power Design Techniques(invited)," Japan Industrial Engineering Center Seminar, Nov. 28, 1995

1994

#1994001
Y. Unekawa, T. Kobayashi, T. Shirotori, Y. Fujimoto, T. Shimazawa, K. Nogami, T. Nakao, K. Sawada, M. Matsui, T. Sakurai, M. K.Tang, and B. Huffman, "A 110-MHz/1-Mb Synchronous TagRAM," IEEE Journal of Solid-State Circuits, Vol.29, No.4, pp.403-410, Apr. 1994 (PDF)

#1994002
M. Matsui, H. Hara, K. Seta, Y. Uetani, L. Kim, T. Nagamatsu, T. Shimazawa, S. Mita, G. Otomo, T. Oto, Y. Watanabe, F. Sano, A. Chiba, K. Matsuda, and T. Sakurai, "200MHz Video Compression Macrocells Using Low-Swing Differential Logic," IEEE International Solid-State Circuits Conference, 4.6, pp.76-77, Feb. 1994 (PDF)

#1994003
T. Demura, T. Oto, K. Kitagaki, S. Ishiwata, G. Otomo, S. Michinaka, N. Goto, M. Matsui, H. Hara, T. Nagamatsu, K. Seta, T. Shimazawa, K. Maeguchi, T. Odaka, Y. Uetani, T. Oku, T. Yamakage, and T. Sakurai, "A Single-Ship MPEG2 Decoder LSI," IEEE International Solid-State Circuits Conference, 4.4, pp.72-73, Feb. 1994 (PDF)

#1994004
A. Parameswar, H. Hara, and T. Sakurai, "A High-Speed, Low-Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications," IEEE Custom Integrated Circuits Conference, pp.278-281, May 1, 1994

#1994005
T. Takayanagi, K. Sawada, T. Sakurai, Y. Parameshwar, S. Tanaka, N. Ikumi, M. Nagamatsu, Y. Kondo, K. Minagawa, J. Brennan, P. Hsu, P. Rodman, J. Bratt, J. Scanlon, M. Tang, C. Joshi, and M. Nofal, "Embedded Memory Design for a Four Issue Superscaler RISC Microprocessor(invited)," IEEE Custom Integrated Circuits Conference, pp.585-590, May 1994

#1994006
T. Kobayashi, and T. Sakurai, "Self-Adjusting Threshold-Voltage Scheme (SATS) for Low-Voltage High-Speed Operation," IEEE Custom Integrated Circuits Conference, pp.271-274, May 1994

#1994007
K. Shimazawa, T. Sakurai et al, "200MHz Video Compression / Decompression Macro-cells using Sense-Amplifying Flip-Flops," Technical Report of IEICE, CPSY94-9, pp.57-64, Apr. 1994

#1994008
G. Ootomo, K. Kitagaki, T. Demura, S. Ishiwata, S. Michinaka, T. Oto, and T. Sakurai, "Development of MPEG2 Video Decoder LSI," Technical Report of IEICE, ICD94-83, pp.25-32, Aug. 1994

#1994009
M. Matsui, H. Hara, Y. Uetani, L. Kim, T. Nagamatsu, Y. Watanabe, A. Chiba, K. Matsuda, and T. Sakurai, "A 200MHz 13mm2 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme," IEEE Journal of Solid-State Circuits, Vol.29, No.12, pp.1482-1490, Dec. 1994 (PDF)

#1994010
I. Young and T. Sakurai, "Future high performance microprocessor implementation tradeoffs," Symposium on VLSI Circuits, Panel discussion, pp.49, June 1994 (PDF)

1993

#1993001
Y. Unekawa, T. Kobayashi, T. Shirotori, Y. Fujimoto, T. Shimazawa, K. Nogami, T. Nakao, K. Sawada, M. Matsui, T. Sakurai, M. K.Tang, and B. Huffman, "A 110MHz/1Mbit Synchronous TagRAM," Symposium on VLSI Circuits, pp.15-16, 1993 (PDF)

#1993002
F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, Y. Hibi, Y. Saeki, H. Muroga, A. Tanaka, and K. Kanzaki, "Introducing Redundancy in Field Programmable Gate Arrays," IEEE Custom Integrated Circuits Conference, pp.7.1.1-7.1.4, May 1993

#1993003
T. Sakurai, "High Speed / High-Density Logic Circuit Design(invited)," International Symposium on VLSI Technology, Systems, and Applications, Taiwan, pp.222-226, May 12-14, 1993

#1993004
T. Sakurai, "High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage(invited)," IEEE International Symposium on Circuit and Systems, Chicago, pp.1487-1490, May 1993 (PDF)

#1993005
T. Sakurai, "Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI's," IEEE Transactions on Electron Devices, Vol.40, No.1, pp.118-124, Jan. 1993 (PDF)

#1993006
T. Sakurai and A. El Gamal, "Multi-million gate ASIC's," Symposium on VLSI Circuits, Panel discussion, pp.95, May 1993 (PDF)

1992

#1992001
T. Sakurai, "A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization," IEEE Journal of Solid-State Circuits, Vol.27, No.7, pp.1014-1019, July 1992 (PDF)

#1992002
H. Hara, T. Sakurai, T. Nagamatsu, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, K. Matsuda, Y. Watanabe, F. Sano, and A. Chiba, "0.5-um 3.3-V BiCMOS Standard Cells with 32-kilobyte Cache and Ten-Port Register File," IEEE Journal of Solid-State Circuits, Vol.27, No.11, pp.1579-1584, Nov. 1992 (PDF)

#1992003
T. Sakurai, "Panel on High Speed I/O," IEEE International Solid-State Circuits Conference, Panel discussion, pp.188, Feb. 1992

#1992004
T. Sakurai, B. Lin and A. R. Newton, "Fast Simulated Diffusion: An Optimization Algorithm for Multi-minimum Problems and Its Application to MOSFET Model Parameter Extraction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.11, No.2, pp.228-234, Feb. 1992 (PDF)

#1992005
H. Hara and T. Sakurai et al., "0.5um BiCMOS Standard-Cell Macros Including 0.5W 3ns Register File and 0.6W 5ns 32kB Cache," International Solid-State Circuits Conference, pp.46-47, Feb. 1992 (PDF)

#1992006
K. Seta, H. Hara, T. Sakurai, T. Nagamatsu, Y. Niitsu, H. Miyakawa, K. Matsuda, Y. Watanabe, F. Sano, and A. Chiba, "0.5um BiCMOS Standard Cell Macro's," Technical Report of IEICE, ED92-57, ICD92-42, pp.1-8, Aug. 1992

#1992007
T. Sakurai and H. Kato, "Topics in ISSCC'92," Semiconductor World, Press Journal, pp.36-39, May 1992

#1992008
T. Mori, T. Sakurai et al., "0.5um BiCMOS ASIC Family," IEEE Custom Integrated Circuits Conference, Session2 New Products - High Performance Devices and Test Methodologies, May 1992

#1992009
T. Mori, T. Sakurai et al., "0.5um BiCMOS ASIC Family," Technical Report of IEICE, CAS92-61, ICD92-99, pp.25-32, Nov. 1992

#1992010
M. Takahashi, T. Sakurai, K. Sawada, K. Nogami, and M. Ichida, "3.3V - 5V Compatible I/O Circuit without Thick Gate Oxide," IEEE Custom Integrated Circuits Conference, pp.23.3.1-23.3.4, May 1992

#1992011
T. Sakurai, "A Review on Low-Voltage BiCMOS Circuits and a BiCMOS vs. CMOS Speed Comparison," 35th Midwest Symposium on Circuits and Systems, Washington DC, pp.564-567, Aug. 1992

1991

#1991001
T. Sakurai and A. R. Newton, "Delay Analysis of Series-Connected MOSFET Circuits," IEEE Journal of Solid-State Circuits, Vol.26, No.2, pp.122-131, Feb. 1991 (PDF)

#1991002
T. Sakurai, S. Kobayashi, and M. Noda, "Simple Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI's," IEEE International Symposium on Circuit and Systems, pp.2375-2378, June 1991

#1991003
T. Sakurai and A. R. Newton, "A Simple Short-Channel MOSFET Model and Its Application to Delay Analysis of Inverters and Series-Connected MOSFET's," IEEE International Symposium on Circuit and Systems, TUAM-3-7, May 1990

#1991004
T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, Vol.38, No.4, pp.887-894, Apr. 1991 (PDF)

#1991005
T. Sakurai, "A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization," IEEE European Solid-State Circuits Conference, pp.129-132, Sep. 1991

#1991006
T. Nagamatsu, T. Sakurai, H. Hara, S. Kobayashi, K. Seta, M. Noda, M. Uchida, Y. Watanabe, and F. Sano, "A 1.9ns BiCMOS CAM Macro with Double Match Line Architecture," IEEE Custom Integrated Circuits Conference, pp.14.3.1-14.3.4, May 1991

#1991007
H. Hara, T. Sakurai, M. Noda, T. Nagamatsu, S. Kobayashi, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, K. Maeguchi, Y. Watanabe, and F. Sano, "0.5um 2M-Transistor BiPNMOS Channelless Gate Array," IEEE International Solid-State Circuits Conference, 9.1, pp.148-149, Feb. 1991 (PDF)

#1991008
T. Sakurai, "Panel on Silicon Integrated Systems Beyond Half Micron," IEEE International Solid-State Circuits Conference, Panel discussion, pp.197, Feb. 1991

#1991009
T. Sakurai, M. Ichida and A. R. Newton, "Fast Simulated Diffusion: An Optimization Algorithm for Multi-Minimum Problems and Its Application to MOSFET Model Parameter Extraction," IEEE Custom Integrated Circuits Conference, pp.8.8.1-8.8.4, May 1991

#1991010
H. Hara, T. Sakurai, H. Miyakawa, K. Seta, and Y. Watanabe, "0.5um 3.3V BiPNMOS Gate Array," Technical Report of IEICE, CAS91-38, SDM91-43, ICD91-47, pp.71-76, June 1991

#1991011
H. Hara, T. Sakurai, M. Noda, T. Nagamatsu, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, and Y. Watanabe, "0.5-um 2M-Transistor BiPNMOS Channelless Gate Array," IEEE Journal of Solid-State Circuits, Vol.26, No.11, pp.1615-1620, Nov. 1991 (PDF)

1990

#1990001
T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and Its Application to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid-State Circuits, Vol.25, No.2, pp.584-594, Apr. 1990 (PDF)

#1990002
T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis and Its Application to CMOS Gate Delay Analysis and Series-Connected MOSFET Structure," Dept. EECS, Univ. of Calif., Berkeley, pp.ERL Memo M90/19, Mar. 1990 (PDF)

#1990003
T. Sakurai and A. R. Newton, "MOSFET Model Parameter Extraction Based on Fast Simulated Diffusion," Dept. EECS, Univ. of Calif., Berkeley, pp.ERL Memo M90/20, Mar. 1990 (PDF)

#1990004
T. Sakurai and A. R. Newton, "Multiple-Output Shared Transistor Logic (MOSTL) Family Synthesized Using Binary Decision Diagram," Dept. EECS, Univ. of Calif., Berkeley, pp.ERL Memo M90/21, Mar. 1990 (PDF)

#1990005
T. Sakurai, "High-Speed Circuit Design," IEEE Custom Integrated Circuits Conference, Educational Session E2.1, May 1990

#1990006
K. Nogami, T. Sakurai, K. Sawada, K. Sakaue, Y. Miyazawa, S. Tanaka, Y. Hiruta, K. Katoh, T. Takayanagi, T. Shirotori, Y. Itoh, M. Uchida, and T. Iizuka, "A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC," IEEE Journal of Solid-State Circuits, Vol.25, No.1, pp.100-108, Feb. 1990 (PDF)

1989

#1989001
K. Nogami, T. Sakurai, K. Sawada, K. Sakaue, Y. Miyazawa, S. Tanaka, Y. Hiruta, K. Katoh, T. Takayanagi, T. Shirotori, Y. Itoh, M. Uchida, and T. Iizuka, "Circuit design of a 9ns-HIT-delay 32K byte cache macro," Symposium on VLSI Circuits, pp.45-46, May 1989 (PDF)

1988

#1988001
T. Sakurai, "Optimization of CMOS Arbiter and Synchronizer with Sub-micron MOSFETs," IEEE Journal of Solid-State Circuits, Vol.23, No.4, pp.901-906, Aug. 1988 (PDF)

#1988002
K. Sawada, T. Sakurai, K. Nogami, T. Iizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, Y. Shiotari, Y. Itabashi, and S. Kohyama, "A 72K CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM," IEEE Custom Integrated Circuits Conference, pp.20.3.1-20.3.4, May 1988 (PDF)

#1988003
T. Sakurai, K. Nogami, K. Sawada, and T. Iizuka, "Transparent-Refresh DRAM (TReD) Using Dual-Port DRAM Cell," IEEE Custom Integrated Circuits Conference, pp.4.3.1-4.3.4, May 1988 (PDF)
(PDF)
#1988004
T. Sakurai, K. Nogami, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maeguchi, K. Kobayashi, T. Ando, Y. Hayakashi, A. Miyoshi, and K. Sato, "A Circuit Design of 32KByte Integrated Cache Memory," Symposium on VLSI Circuits, pp.45-46, Aug. 1988 (PDF)

#1988005
K. Nogami, T. Sakurai, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maeguchi, K. Kobayashi, T. Ando, Y. Hayakashi, A. Miyoshi, and K. Sato, "Architecture and Design Methodology of 32KByte Integrated Cache Memory," IEEE European Solid-State Circuits Conference, Sep. 1988

#1988006
T. Sakurai, K. Nogami, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maeguchi, K. Kobayashi, T. Ando, Y. Hayakashi, A. Miyoshi, and K. Sato, "32KByte Integrated Cache Memory," “dŽq’ʐMŠw‰ï H‹G‘å‰ï, Sep. 1988

#1988007
K. Sawada, T. Sakurai, K. Nogami, T. Iizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, Y. Shiotari, Y. Itabashi, and S. Kohyama, "1Mbit Dynamic RAM embedded in 72K CMOS Track-Free Gate Array," “dŽq’ʐMŠw‰ï H‹G‘å‰ï, Sep. 1988

#1988008
T. Sakurai, K. Nogami, K. Sawada, and T. Iizuka, "Transparent-Refresh DRAM Macro for ASMIC," “dŽq’ʐMŠw‰ï H‹G‘å‰ï, Sep. 1988

#1988009
T. Iizuka, T. Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, M. Ogura, K. Kobayashi, and A. Miyoshi, "Technical Trend of Application Specific Memory," “dŽq’ʐMŠw‰ï H‹G‘å‰ï, Sep. 1988

#1988010
T. Iizuka, T. Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, and T. Miyoshi, "Large Memory Embedded ASICs (Invited)," International Conference on Computer Design, Dec. 1988

#1988011
T. Sakurai, "CMOS Inverter Delay and Other Analytical Formulas Using a-Power Law MOS Model," International Conference on Computer Aided Design, pp.74-77, Nov. 1988 (PDF)

1987

#1987001
T. Sakurai, "Panel on Digital ICs with Embedded Memory," IEEE International Solid-State Circuits Conference, Panel discussion, pp.239, Feb. 1987

#1987002
T. Sakurai, K. Sawada, K. Nogami, T. Wada, K. Sato, M. Kakumu, S. Morita, M. Kinugawa, T. Asami, K. Narita, J. Matsunage, A. Higuchi, and T. Iizuka, "A 36ns 1Mbit Pseudo SRAM with VSRAM mode," Symposium on VLSI Circuits, pp.45-46, May 1987 (PDF)

#1987003
K. Nogami, K. Sawada, M. Kinugawa, and T. Sakurai, "VLSI Circuit Reliability under AC Hot-Carrier Stress," Symposium on VLSI Circuits, pp.13-14, May 1987 (PDF)

#1987004
T. Sakurai, "Simulation Technique for Developing Ultra High Speed MOS LSI," Three Hour Lecture held by Giken-Joho Center, June 22, 1986

#1987005
K. Sawada, T. Sakurai, K. Nogami, T. Shirotori, M. Isobe, A. Higuchi, and T. Iizuka, "Design and Evaluation of 1Mbit Pseudo/Virtually Static RAM," “dŽq’ʐMŠw‰ï ‰ņ˜H‚ƃVƒXƒeƒ€ŒĪ‹†‰ï, CAS87-108, Aug. 1987

#1987006
T. Sakurai, K. Sawada, and K. Nogami, "Optimization of CMOS Arbiter/Synchronizer and Its Application to Submicron Devices," “dŽq’ʐMŠw‰ï ‰ņ˜H‚ƃVƒXƒeƒ€ŒĪ‹†‰ï, CAS87-107, Aug. 1987 (PDF)

#1987007
K. Nogami and T. Sakurai, "A Drivability Compensated Output Buffer," “dŽq’ʐMŠw‰ï ‘‡‘å‰ï, pp.1-130, Oct. 1987

#1987008
K. Sawada, T. Sakurai, K. Nogami, K. Sato, T. Shirotori, M. Kakumu, S. Morita, M. Kinugawa, T. Asami, K. Narita, J. Matsunaga, A. Higuchi, and T. Iizuka, "A 30-uA Data-Retention Pseudostatic RAM with Virtually Static RAM Mode," IEEE Journal of Solid-State Circuits, Vol.23, No.1, pp.12-19, Feb. 1988 (PDF)

#1987009
T. Sato, N. Yamada, and T. Sakurai, "Topics of ISSCC'87," Denshi-Zairyou, pp.139-145, June 1987

#1987010
K. Sawada, T. Sakurai, K. Nogami, T. Shirotori, M. Isobe, A. Higuchi, and T. Iizuka, "Design and Evaluation of 1Mbit Pseudo/Virtually Static RAM," Circuit and System Research Group of IECE of Japan, CAS87-108, Aug. 1987

#1987011
T. Sakurai, "Problems and Solutions for MOS LSI Circuit Simulation," Three Hour Lecture, Giken-Joho Center, July 23, 1986

#1987012
D. R.Asdsen, J. J.Barnes, B. Barton, S. Chan, D. Draper, P. A.Reed, T. Sakurai, "Digital ICs with Embedded Memory," IEEE International Solid-State Circuits Conference, International discussion 6, Feb. 26, 1987 (PDF)
(PDF)

1986

#1986001
T. Sakurai, K. Sawada, K. Nogami, T. Wada, M. Isobe, M. Kakumu, S. Morita, M. Yokogawa, M. Kinugawa, T. Asami, K. Hashimoto, J. Matsunage, H. Nozawa, and T. Iizuka, "A 1Mb Virtually SRAM," IEEE International Solid-State Circuits Conference, pp.252-253, Feb. 1986 (PDF)

#1986002
T. Sakurai, K. Nogami, M. Kakumu, and T. Iizuka, "Hot-Carrier Generation in Submicrometer VLSI Environment," IEEE Journal of Solid-State Circuits, Vol.21, No.1, pp.187-192, Feb. 1986 (PDF)

#1986003
K. Nogami, T. Sakurai, K. Sawada, T. Wada, M. Isobe, M. Kakumu, S. Morita, M. Yokogawa, M. Kinugawa, T. Asami, K. Hashimoto, J. Matsunage, H. Nozawa, and T. Iizuka, "A 1Mb Virtually Static RAM," IEEE Journal of Solid-State Circuits, Vol.21, No.5, pp.662-669, Oct. 1986 (PDF)

#1986004
K. Sawada, T. Sakurai, K. Nogami, T. Wada, M. Isobe, and T. Iizuka, "Self-Aligned Refresh Scheme for VLSI Intelligent Dynamic RAMs," Symposium on VLSI Technology, pp.85-86, May 1986 (PDF)
(PDF)

#1986005
T. Sakurai, T. Furuyama, and T. Sato, "Remarkable Papers in ISSCC'86," Denshi-Zairyou, pp.123-129, June 1986

#1986006
T. Sakurai, M. Kakumu, and K. Sato, "1Mbit Virtually Static RAM," Toshiba Review, 41, 3, pp.227-230, 1986 (PDF)
(PDF)

#1986007
T. Sakurai, "Practical Example of VLSI Circuit Simulation," Three Hour Lecture held by Giken-Joho Center, Dec. 5, 1986

#1986008
ũˆä‹MN, ‘ō“c˜aG, –ėãˆęF, ˜a“c“N“T, ˆé•”–ž˜Y, ”Ņ’Ë“NÆ, "Virtually Static RAM‚ÆŠeŽíRAM‚Ė”äŠr," “dŽqî•ņ’ʐMŠw‰ï ‘‡‘S‘‘å‰ï, 1986 (PDF)
(PDF)

1985

#1985001
T. Sakurai, M. Kakumu, and T. Iizuka, "Hot-Carrier Suppressed VLSI with Submicron Geometry," IEEE International Solid-State Circuits Conference, pp.272-273, Feb. 1985 (PDF)

#1985002
T. Sakurai and T. Iizuka, "Modeling of Substrate Current in MOS Circuit," ‰ž—p•Ļ—Šw‰ï t‹Gu‰‰‰ï, pp.559, Mar. 1985

#1985003
T. Sakurai and T. Iizuka, "Gate Electrode RC Delay Effects in VLSI's," IEEE Journal of Solid-State Circuits, Vol.20, No.1, pp.290-294, Feb. 1985 (PDF)

#1985004
T. Sakurai and T. Iizuka, "Gate Electrode RC Delay Effects in VLSI's," IEEE Transactions on Electron Devices, Vol.32, No.2, pp.370-374, Feb. 1985 (PDF)

#1985005
K. Sawada, T. Sakurai, and T. Iizuka, "On-Chip Battery Backup Circuit for VLSI Static RAMs," International Conference on Solid State Devices and Materials, pp.49-52, 1985

#1985006
T. Sakurai, K. Nogami, and T. Iizuka, "A New Method for CMOS Circuit Delay Estimation," ‰ž—p•Ļ—Šw‰ï H‹Gu‰‰‰ï, pp.495, 1985

#1985007
T. Iizuka, T. Sakurai, and M. Kakumu, "Circuit Cleverness for Protecting MOSFETs from Hot-Carriers," “úŒoƒ}ƒCƒNƒƒfƒoƒCƒX, Summer Issue, pp.39-54, June 1985

#1985008
K. Hashimoto, Y. Nagakubo, S. Yokogawa, M. Kakumu, M. Kinugawa, K. Sawada, T. Sakurai, M. Isobe, J. Matsunage, and T. Iizuka, "Deep Trench Well Isolation for 256Kbit CMOS Static RAM," Symposium on VLSI Technology, pp.94-95, May 1985

#1985009
K. Nogami, K. Sawada, T. Sakurai, T. Wada, M. Isobe, and T. Iizuka, "Electron-Beam Tester Evaluation of 1Mbit VSRAM," “dŽq’ʐMŠw‰ï ‘‡‘å‰ï, pp.2-226, 1985

#1985010
T. Sakurai, K. Sawada, K. Nogami, T. Wada, M. Isobe, and T. Iizuka, "Comparison of Virtually Static RAM and Other RAMs," “dŽq’ʐMŠw‰ï ‘‡‘å‰ï, 1985

#1985011
T. Sakurai, K. Nogami, M. Kakumu, and T. Iizuka, "Analysis of Hot Substrate Current Generation in MOS Circuits," Japan Semiconductor Technology Reports, 1, 1, pp.65-67, 1985

1984

#1984001
T. Sakurai and T. Iizuka, "Gate Electrode RC Delay Effects," “dŽq’ʐMŠw‰ï ‘‡‘å‰ï, pp.437, 1984 (PDF)

#1984002
K. Sawada, T. Sakurai, and T. Iizuka, "Access Time Analysis of CMOS Static RAMs," “dŽq’ʐMŠw‰ï ‘‡‘å‰ï, pp.511, 1984

#1984003
T. Sakurai and T. Iizuka, "Measurement of Junction Capacitance using Voltage Followers," ‰ž—p•Ļ—Šw‰ï t‹Gu‰‰‰ï, pp.483, 1984

#1984004
T. Sakurai, K. Sawada, and T. Iizuka, "VLSI-oriented Dual Voltage Down Conversion Circuits," ‰ž—p•Ļ—Šw‰ï H‹Gu‰‰‰ï, pp.411, 1984

#1984005
K. Sawada, T. Sakurai, T. Ohtani, M. Isobe, and T. Iizuka, "Electron-Beam Tester Evaluation of 256Kbit CMOS Static RAM with Dynamic Double Word Line," ‰ž—p•Ļ—Šw‰ï H‹Gu‰‰‰ï, pp.389, 1984

#1984006
T. Sakurai, K. Sawada, and T. Iizuka, "VLSI-oriented Voltage Down Conversion Circuits with Sub-Main Configuration," Late News Abstract of the International Conference on Solid State Devices & Materials, LC-12-7, pp.74, 1984 (PDF)

#1984007
K. Sawada, T. Sakurai, T. Ohtani, M. Isobe, and T. Iizuka, "Pursuit of High Performance High Density SRAM -- Dynamic Double Word Line Approach," “dŽq’ʐMŠw‰ï ”ž“ą‘ĖƒfƒoƒCƒXEƒgƒ‰ƒ“ƒWƒXƒ^ŒĪ‹†‰ï, SSD84-22, pp.59-64, May 1984

#1984008
M. Isobe, J. Matsunaga, T. Sakurai, T. Ohtani, K. Sawada, H. Nozawa, T. Iizuka, and S. Kohyama, "A 46ns 256Kbit CMOS SRAM," IEEE International Solid-State Circuits Conference, pp.214-215, Feb. 1984 (PDF)

#1984009
T. Sakurai, J. Matsunaga, M. Isobe, T. Ohtani, K. Sawada, A. Aono, H. Nozawa, T. Iizuka, and S. Kohyama, "A Low Power 46 ns 256 kbit CMOS SRAM with Dynamic Double Word Line," IEEE Journal of Solid-State Circuits, Vol.19, No.5, pp.578-585, Oct. 1984 (PDF)

#1984010
K. Sawada, T. Sakurai, T. Ohtani, M. Isobe, and T. Iizuka, "Electron-Beam Tester Evaluation of 256Kbit CMOS Static RAM," Gakujutsu Shinkokai of Japan, pp.35-38, 1984

1983

#1983001
T. Sakurai and K. Tamaru, "Simple Formulas for Two- and Three-Dimensional Capacitances," IEEE Transactions on Electron Devices, Vol.30, No.2, pp.183-185, Feb. 1983 (PDF)

#1983002
T. Sakurai, "Approximation of Wiring Delay in MOSFET LSI," IEEE Journal of Solid-State Circuits, Vol.18, No.4, pp.418-425, Aug. 1983 (PDF)

#1983003
T. Sakurai and T. Iizuka, "Double Word Line and Bit Line Structure for VLSI RAMs -- Reduction of Word Line Delay and Bit Line Delay," International Conference on Solid State Devices and Materials, Tokyo, (A-7-6), pp.269-272, 1983 (PDF)

#1983004
T. Iizuka and T. Sakurai, "CR Isolated Cell for Soft Error Prevention -- Static RAM Application," Symposium on VLSI Technology, Hawaii, pp.70-71, May 1983 (PDF)

1982

#1982001
T. Sakurai, T. Furuyama, and T. Iizuka, "Analysis of Word Line Delay and Its Application," Semiconductor Device & Transistor Research Group of IECE of Japan, SSD82-72, pp.15-22, 1982 (PDF)

1981

#1981001
T. Sakurai, "Electronic Structure of Si-SiO2 System," Ph.D Dissertation, Tokyo Univ., Feb. 1981

1980

#1980001
T. Sakurai and T. Sugano, "Tight-Binding Studies of Si-SIO2 System," Annual Technical Report of Tokyo University, 39, 1979

#1980002
T. Sakurai and T. Sugano, "Studies on Electronic Structures of Crystal Free Surface by Layer Stacking Method," ‰ž—p•Ļ—Šw‰ï t‹Gu‰‰‰ï, pp.558, 1980

#1980003
T. Sakurai and T. Sugano, "Theoretical Calculation of Electronic Structures for Crystalline Si and Amorphous SiO2 System," ‰ž—p•Ļ—Šw‰ï H‹Gu‰‰‰ï, 1980

#1980004
T. Sakurai and T. Sugano, "Theoretical Calculation of Electronic Structures for Crystalline Si and Amorphous SiO2 Interface," “dŽq’ʐMŠw‰ï “dŽqƒfƒoƒCƒXŒĪ‹†‰ï, ED80-64, 1980

#1980005
T. Sakurai and T. Sugano, "Gap States of Crystalline Silicon and Amorphous SiO2 System," Conference on Physics of MOS Insulators, North Carolina, June 1980

#1980006
T. Sakurai and T. Sugano, "Theory of Continuously Distributed Trap States at Si-SiO2 Interfaces," Journal of Applied Physics, Vol.52(4), No., pp.2889-1296, Apr. 1981 (PDF)

1979

#1979001
T. Sakurai and H. Yanai, "Numerical Analysis of Merged Semiconductor Devices," Journal of IECE of Japan, J62-C, 1, pp.62, Jan. 1979

#1979002
T. Sakurai and T. Sugano, "Determination of Extended Huckel Parameters for SiO2," ‰ž—p•Ļ—Šw‰ï H‹Gu‰‰‰ï, pp.484, Aug. 1979

1978

#1978001
T. Sakurai, "Numerical Analysis Method for Merged Semiconductor Devices," Master Dissertation, Tokyo Univ., Feb. 1978


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