The Japanese version is here.

H. Fuketa, K. Yoshioka, T. Yokota, W. Yukita, M. Koizumi, M. Sekino, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "Organic-Transistor-Based 2kV ESD-Tolerant Flexible Wet Sensor Sheet for Biomedical Applications with Wireless Power and Data Transmission Using 13.56MHz Magnetic Resonance," IEEE International Solid-State Circuits Conference (ISSCC), pp. 490-491, Feb. 2014.

#2014001

H. Fuketa, M. Nomura, M. Takamiya, and T. Sakurai, "Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits," IEEE Journal of Solid-State Circuits, Vol.49, No.2, pp. 536-544, Feb. 2014.

X. Zhang, Y. Okuma, P. -H. Chen, K. Ishida, Y. Ryu, K. Watanabe, T. Sakurai, and M. Takamiya, "A 0.6-V Input 94% Peak Efficiency CCM/DCM Digital Buck Converter in 40-nm CMOS with Dual-Mode-Body-Biased Zero-Crossing Detector," IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 45-48, Nov. 2013.

#2013015

H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Variation-aware Subthreshold Logic Circuit Design," IEEE International Conference on ASIC (ASICON), pp. 95-98, Oct. 2013. (Invited)

#2013014

K. Mori, Y. Okuma, X. Zhang, H. Fuketa, T. Sakurai, and M. Takamiya, "Analog-Assisted Digital Low Dropout Regulator (AAD-LDO) with 59% Faster Transient Response and 28% Ripple Reduction," International Conference on Solid State Devices and Materials (SSDM), pp. 888-889, Sep. 2013.

#2013013

H. Fuketa, R. Takahashi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits," IEEE Journal of Solid-State Circuits, Vol. 48, No. 8, pp. 1986-1994, Aug. 2013.

#2013012

H. Fuketa, K. Ishida, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "Large-Area and Flexible Sensors with Organic Transistors," IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), pp. 87-90, June 2013. (Invited)

#2013011

S. Iguchi, A. Saito, Y. Zheng, K. Watanabe, T. Sakurai, and M. Takamiya, "93% Power Reduction by Automatic Self Power Gating (ASPG) and Multistage Inverter for Negative Resistance (MINR) in 0.7V, 9.2uW, 39MHz Crystal Oscillator," IEEE Symposium on VLSI Circuits, pp. C142-C143, June 2013.

#2013010

M. Nomura, A. Muramatsu, H. Takeno, S. Hattori, D. Ogawa, M. Nasu, K. Hirairi, S. Kumashiro, S. Moriwaki, Y. Yamamoto, S. Miyano, Y. Hiraku, I. Hayashi, K. Yoshioka, A. Shikata, H. Ishikuro, M. Ahn, Y. Okuma, X. Zhang, Y. Ryu, K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, and T. Sakurai, "0.5V Image Processor with 563 GOPS/W SIMD and 32bit CPU Using High Voltage Clock Distribution (HVCD) and Adaptive Frequency Scaling (AFS) with 40nm CMOS," IEEE Symposium on VLSI Circuits, pp. C36-C37, June 2013.

#2013009

H. Fuketa, K. Hirairi, T.Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 6, pp. 1175-1179, June 2013.

#2013008

S. Iguchi, P. Yeon, H. Fuketa, K. Ishida, T. Sakurai, and M. Takamiya, "Zero Phase Difference Capacitance Control (ZPDCC) for Magnetically Resonant Wireless Power Transmission," IEEE Wireless Power Transfer Conference (WPTC), pp. 25-26, May. 2013.

#2013007

H. Fuketa, Y. Shinozuka, K. Ishida, M. Takamiya, T. Fujii, H. Shimizu, K. Kobayashi, T. Sato, and T. Sakurai, "Efficiency Increase in On-Chip Buck Converter by Introduction of High Permeability Material to Inductor on Interposer," International Conference on Ferrites (ICF), p. 75, Apr. 2013.

#2013006

Y. Shinozuka, H. Fuketa, K. Ishida, F. Furuta, K. Osada, K. Takeda, M. Takamiya, and T. Sakurai, "Reducing IR Drop in 3D Integration to Less Than 1/4 Using Buck Converter on Top Die (BCT) Scheme," IEEE International Symposium on Quality Electronic Design (ISQED), pp. 210-215, March 2013.

#2013005

H. Fuketa, M. Nomura, M. Takamiya, T. Sakurai, "Intermittent Resonant Clocking Enabling Power Reduction at any Clock Frequency for 0.37V 980kHz Near-Threshold Logic Circuits," IEEE International Solid-State Circuits Conference (ISSCC), pp. 436-437, Feb. 2013.

#2013004

H. Fuketa, K. Yoshioka, Y. Shinozuka, K. Ishida, T. Yokota, N. Matsuhisa, Y. Inoue, M. Sekino, T. Sekitani, M. Takamiya, T. Someya, T. Sakurai, "1um-Thickness 64-Channel Surface Electromyogram Measurement Sheet with 2V Organic Transistors for Prosthetic Hand Control," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2013.

#2013003

S. Iguchi, A. Saito, K. Honda, Y. Zheng, K. Watanabe, T. Sakurai, and M. Takamiya, "315MHz OOK Transceiver with 38-uW Receiver and 36-uW Transmitter in 40-nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 93-94, Jan. 2013.

#2013002

X. Zhang, P. -H. Chen, Y. Ryu, K. Ishida, Y. Okuma, K. Watanabe, T. Sakurai, and M. Takamiya, "A Low Voltage Buck DC-DC Converter Using On-Chip Gate Boost Technique in 40nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), pp. 109-110, Jan. 2013.

#2013001

K. Ishida, T.-C. Huang, K. Honda, Y. Shinozuka, H. Fuketa, T. Yokota, U. Zschieschang, H. Klauk, G. Tortissier, T. Sekitani, M. Takamiya, H. Toshiyoshi, T. Someya, and T. Sakurai, "Insole Pedometer With Piezoelectric Energy Harvester and 2V Organic Circuits," IEEE Journal of Solid-State Circuits, Vol.48, No.1, pp. 255-264, Jan. 2013.

X. Zhang, P. -H. Chen, Y. Ryu, K. Ishida, Y. Okuma, K. Watanabe, T. Sakurai, and M. Takamiya, "A 0.45-V Input On-Chip Gate Boosted (OGB) Buck Converter in 40-nm CMOS with More Than 90% Efficiency in Load Range from 2uW to 50uW," IEEE Symposium on VLSI Circuits, Hawaii, pp. 194-195, June 2012.

[Paper Link]

#2012012

A. Saito, K. Honda, Y. Zheng, S. Iguchi, K. Watanabe, T. Sakurai, and M. Takamiya, "An All 0.5V, 1Mbps, 315MHz OOK Transceiver with 38-uW Carrier-Frequency-Free Intermittent Sampling Receiver and 52-uW Class-F Transmitter in 40-nm CMOS," IEEE Symposium on VLSI Circuits, Hawaii, pp. 38-39, June 2012.

[Paper Link]

#2012011

N. Masunaga, K. Ishida, T. Sakurai, and M. Takamiya, "EMI Camera LSI(EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution," IEICE Transaction on Electronics, E95-C, No.6, pp. 1059-1066, June 2012.

[Paper Link]

#2012010

L. Liu, T. Sakurai, and M. Takamiya, "A 315MHz Power-Gated Ultra Low Power Transceiver in 40nm CMOS for Wireless Sensor Network," IEICE Transaction on Electronics, E95-C, No.6, pp. 1035-1041, June 2012.

[Paper Link]

#2012009

H. Lim, K. Ishida, M. Takamiya, and T. Sakurai, "Positioning-Free Magnetically Resonant Wireless Power Transmission Board with Staggered Repeater Coil Array (SRCA)," IEEE MTT-S International Microwave Workshop Series on Innovative Wireless Power Transmission: Technologies, Systems, and Applications (IMWS-IWPT), Kyoto, pp. 93-96, May 2012.

[Paper Link]

#2012008

P. -H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and Vth-Tuned Oscillator With Fixed Charge Programming," IEEE Journal of Solid-State Circuits, Vol.47, No.5, pp. 1252-1260, May. 2012.

[Paper Link]

#2012006

T. Yasufuku, K. Hirairi, Y. Pu, Y. -F. Zheng, R. Takahashi, M. Sasaki, H. Fuketa, A. Muramatsu, M. Nomura, F. Shinohara, M. Takamiya, and T. Sakurai, "24% Power Reduction by Post-Fabrication Dual Supply Voltage Control of 64 Voltage Domains in VDDmin Limited Ultra Low Voltage Logic Circuits," IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, USA, pp. 586-591, March 2012.

[Paper Link]

#2012005

K. Hirairi, Y. Okuma, H. Fuketa, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "13% Power Reduction in 16b Integer Unit in 40nm CMOS by Adaptive Power Supply Voltage Control with Parity-Based Error Prediction and Detection (PEPD) and Fully Integrated Digital LDO," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 486-487, Feb. 2012.

[Paper Link]

#2012004

K. Ishida, T. -C. Huang, K. Honda, Y. Shinozuka, H. Fuketa, T. Yokota, U. Zschieschang, H. Klauk, G. Tortissier, T. Sekitani, M. Takamiya, H. Toshiyoshi, T. Someya, and T. Sakurai, "Insole Pedometer With Piezoelectric Energy Harvester and 2V Organic Digital and Analog Circuits," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 308-309, Feb. 2012.

[Paper Link]

#2012003

K. Ikeuchi, M. Takamiya, and T. Sakurai, "Through Silicon Capacitive Coupling (TSCC) Interface for 3D Stacked Dies," IEEE International Conference on 3D System Integration (3D IC), P-2-5, Osaka, Feb. 2012.

[Paper Link]

#2012002

P. -H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 120-mV Input, Fully Integrated Dual-Mode Charge Pump in 65-nm CMOS for Thermoelectric Energy Harvester," Asia-South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, pp. 469-470, Jan. 2012.

[Paper Link]

#2012001

K. Ishida, T. -C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda, M. Takamiya, T. Someya, and T. Sakurai, "A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier," IEEE Journal of Solid-State Circuits, Vol.47, No.1, pp. 301-309, Jan. 2012.

[Paper Link]

T. -C. Huang, K. Ishida, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "A Floating-Gate OTFT-Driven AMOLED Pixel Circuit for Variation and Degradation Compensation in Large-Sized Flexible Displays," International Display Workshop (IDW), Nagoya, Japan, pp. 1643-1646, Dec. 2011. (Invited)

[Paper Link]

#2011045

H. Fuketa, T. Yasufuku, S. Iida, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Device-Circuit Interactions in Extremely Low Voltage CMOS Designs," IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, pp. 559-562, Dec. 2011. (Invited)

[Paper Link]

#2011044

T. Yokota, T. Sekitani, T. Tokuhara, U. Zschieschang, H. Klauk, T.-C. Huang, M. Takamiya, T. Sakurai, and T. Someya, "Sheet-type Organic Active Matrix Amplifier System Using Vth-Tunable, Pseudo-CMOS Circuits with Floating-gate Structure," IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, pp. 335-338, Dec. 2011.

#2011043

P. -H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 80-mV Input, Fast Startup Dual-Mode Boost Converter with Charge-Pumped Pulse Generator for Energy Harvesting," IEEE Asian Solid-State Circuits Conference (A-SSCC), Jeju, Korea, pp. 33-36, Nov. 2011.

[Paper Link]

2011 #2011041

M. Daito, Y. Nakata, S. Sasaki, H. Gomyo, H. Kusamitsu, Y. Komoto, K. Iizuka, K. Ikeuchi, G. -S. Kim, M. Takamiya, and T. Sakurai, "Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing," IEEE Journal of Solid-State Circuits, Vol.46, No.10, pp. 2386-2395, Oct. 2011.

[Paper Link]

#2011037

A. Muramatsu, T. Yasufuku, M. Nomura, M. Takamiya, H. Shinohara, and T. Sakurai, "12% Power Reduction by Within-Functional-Block Fine-Grained Adaptive Dual Supply Voltage Control in Logic Circuits with 42 Voltage Domains," 37th European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland, pp. 191-194, Sep. 2011.

[Paper Link]

#2011033

K. Ishida, T. -C. Huang, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, " Large-Area Flexible Electronics with Organic Transistors," IEEE International Midwest Symposium on Circuits and Systems, Seoul, Korea, pp. 1-4, Aug. 2011. (Invited)

[Paper Link]

#2011032

K. Honda, K. Ikeuchi, M. Nomura, M. Takamiya, and T. Sakurai, "Reduction of Minimum Operating Voltage (VDDmin) of CMOS Logic Circuits with Post-Fabrication Automatically Selective Charge Injection," International Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, pp. 175-180, Aug. 2011.

[Paper Link]

#2011031

H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "12.7-times Energy Efficiency Increase of 16-bit Integer Unit by Power Supply Voltage (VDD) Scaling from 1.2V to 310mV Enabled by Contention-less Flip-Flops (CLFF) and Separated VDD between Flip-Flops and Combinational Logics," International Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, pp. 163-168, Aug. 2011.

[Paper Link]

#2011030

T. Yasufuku, S. Iida, H. Fuketa, K. Hirairi, M. Nomura, M. Takamiya, and T. Sakurai, " Investigation of Determinant Factors of Minimum Operating Voltage of Logic Gates in 65-nm CMOS," International Symposium on Low Power Electronics and Design (ISLPED), Fukuoka, Japan, pp. 21-26, Aug. 2011.

[Paper Link]

#2011028

X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P. -H. Chen, K. Watanabe, T. Sakurai, and M. Takamiya, "A Voltage-Reference-Free Pulse Density Modulation (VRF-PDM) 1-V Input Switched-Capacitor 1/2 Voltage Converter with Output Voltage Trimming by Hot Carrier Injection and Periodic Activation Scheme," IEEE Symposium on VLSI Circuits, Kyoto, pp. 280-281, June 2011.

[Paper Link]

#2011027

L. Liu, T. Sakurai, and M. Takamiya, "315MHz Energy-Efficient Injection-Locked OOK Transmitter and 8.4 uW Power-Gated Receiver Front-End for Wireless Ad Hoc Network in 40nm CMOS," IEEE Symposium on VLSI Circuits, Kyoto, pp. 164-165, June 2011.

[Paper Link]

#2011026

H. Fuketa, S. Iida, T. Yasufuku, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "A Closed-Form Expression for Estimating Minimum Operating Voltage (VDDmin) of CMOS Logic Gates," ACM Design Automation Conference, San Diego, USA, pp. 984-989, June 2011.

[Paper Link]

#2011025

T. Yasufuku, Y. Nakamura, Z. Piao, M. Takamiya, and T. Sakurai, "Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout," IEICE Transaction on Electronics, E94-C, No.6, pp. 1072-1075, June 2011.

[Paper Link]

#2011024

K. Ikeuchi, H. Kusamitsu, M. Daito, G. -S. Kim, M. Takamiya, and T. Sakurai, "1 Gb/s, 50um X 50um Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling," IEICE Transaction on Electronics, E94-C, No.6, pp. 992-998, June 2011.

[Paper Link]

#2011023

L. Liu, T. Sakurai. and M. Takamiya, "0.6V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver," IEICE Transaction on Electronics, E94-C, No.6, pp. 985-991, June 2011.

[Paper Link]

#2011022

X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P. -H. Chen, T. Sakurai, and M. Takamiya, "A Variable Output Voltage Switched- Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage," IEICE Transaction on Electronics, E94-C, No.6, pp. 953-959, June 2011.

[Paper Link]

#2011021

Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P. -H. Chen, K. Watanabe, M. Takamiya, and T. Sakurai, "0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS," IEICE Transaction on Electronics, E94-C, No.6, pp. 938-944, June 2011.

[Paper Link]

#2011020

K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD," IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp. 1478-1487, June 2011.

[Paper Link]

#2011019

L. Liu, T. Sakurai, and M. Takamiya, "A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power-and Area-Efficient PLL for Impulse Radio UWB Receiver," IEEE Journal of Solid-State Circuits, Vol.46, No.6, pp. 1349-1359, June 2011.

[Paper Link]

#2011016

T. -C. Huang, K. Ishida, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "A Floating-Gate OTFT-Driven AMOLED Pixel Circuit for Variation and Degradation Compensation in Large-Sized Flexible Displays," Society for Information Display (SID) International Symposium, Los Angeles, USA, pp. 149-152, May 2011.

[Paper Link]

#2011015

Y. Pu, X. Zhang, K. Ikeuchi, A. Muramatsu, A. Kawasumi, M. Takamiya, M. Nomura, H. Shinohara, and T. Sakurai, "Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits," IEEE Transactions on Circuits and Systems-II, Vol. 58, No. 5, pp. 294-298, May 2011.

[Paper Link]

#2011014

T. Yokota, T. Nakagawa, T. Sekitani, Y. Noguchi, K. Fukuda, U. Zschieschang, H. Klauk, K. Takeuchi, M. Takamiya, T. Sakurai, and T. Someya, "Control of Threshold Voltage in Low-Voltage Organic Complementary Inverter Circuits with Floating Gate Structures," Applied. Physics. Letters, 98, 193302, May 2011.

#2011013

P. -H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications," IEICE Transaction on Electronics, E94-C, No.4, pp.598-604, Apr. 2011.

[Paper Link]

#2011005

K. Ishida, T. -C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda, M. Takamiya, T. Someya, and T. Sakurai, "100-V AC Power Meter System-on-a-Film (SoF) Integrating 20-V Organic CMOS Digital and Analog Circuits with Floating Gate for Process Variation Compensation and 100-V Organic PMOS Rectifier," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 218-219, Feb. 2011.

[Paper Link]

#2011004

P. -H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 95mV-Startup Step-up Converter with VTH-Tuned Oscillator by Fixed-Charge Programming and Capacitor Pass-On Scheme," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 216-217, Feb. 2011.

[Paper Link]

#2011003

K. Johguchi, T. Hatanaka, K. Ishida, T. Yasufuku, T. Takamiya, T. Sakurai, and K. Takeuchi, "Through-Silicon Via Design for a 3-D Solid-State Drive System With Boost Converter in a Package," IEEE Transaction on Components, Packaging and Manufacturing Technology, Vol.1, No.2, pp. 269-277, Feb. 2011.

#2011002

X. Zhang, K. Ishida, M. Takamiya, and T. Sakurai, "An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 109-110, Jan. 2011.

[Paper Link]

#2011001

K. Ishida, N. Masunaga, R. Takahashi, T. Sekitani, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "User Customizable Logic Paper (UCLP) with Sea-of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects," IEEE Journal of Solid-State Circuits, Vol.46, No.1, pp. 285-292, Jan. 2011.

[Paper Link]

T. Yasufuku, T. Niiyama, Z. Piao, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, "Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits ," IEICE Transaction on Electronics, E93-C, No.3, pp.332-339, March 2010

[Paper Link]

#2010002

Yasufuku, K. Ishida, S. Miyamoto, H. Nakai, M. Takamiya, and T. Sakurai, "Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories ," IEICE Transaction on Electronics, E93-C, No.3, pp.317-323, March 2010

#2010003

K. Ishida, N. Masunaga, Z. Zhou, T. Yasufuku, T. Sekitani, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "Stretchable EMI Measurement Sheet With 8 X 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 um Silicon CMOS LSIs for Electric and Magnetic Field Detection," IEEE Journal of Solid-State Circuits, Vol. 45, No. 1, pp. 249-259, Jan. 2010

[Paper Link]

#2010004

M. Takamiya, K. Onizuka, K. Ishida, and T. Sakurai, "DC-DC Converter Technologies for On-Chip Distributed Power Supply Systems - 3D Stacking and Hybrid Operation," Springer, pp. 221-247, 2010

#2010005

Y. Kato, T. Sekitani, Y. Noguchi, T. Yokota, M. Takamiya, T. Sakurai and T, Someya, "Large-Area Flexible Ultrasonic Imaging System With an Organic Transistor Active Matrix," IEEE Transactions on Electron Devices, Vol. 57, No. 5, pp. 995 - 1002, 2010

[Paper Link]

#2010006

L. Liu, Z. Zhou, T. Sakurai, and M. Takamiya, "A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS," IEICE Transaction on Electronics, E93-C, No.6, pp. 796-802, 2010

[Paper Link]

#2010014

K. Ishida, N. Masunaga, R. Takahashi, T. Sekitani, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "User Customizable Logic Paper (UCLP) with Sea-of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects," IEEE Journal of Solid-State Circuits, Vol.46, No.1, pp. 285-292, 2011

[Paper Link]

#2010015

L. Liu, T. Sakurai, and M. Takamiya, "A Charge-Domain Auto- and Cross-Correlation Based IR-UWB Receiver with Power- and Area-efficient PLL for 62.5ps Step Data Synchronization in 65nm CMOS," IEEE Symposium on VLSI Circuits, Hawaii, pp. 27-28, 2010

[Paper Link]

#2010016

H. Ishizaki, T. Araki, S. Takahashi, J. Ryu, S. Uchida, N. Yoshida, M. Takamiya and M. Mizuno, "FDM-based Wireless Source Synchronous 15-Mbps TRx with PLL-less Receiver and 1-mm On-chip Integrated Antenna for 1.25-cm Touch-and-Proceed Communication," IEEE Symposium on VLSI Circuits, Hawaii, pp. 73-74, 2010

#2010017

T. Hatanaka, K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai and K. Takeuchi, "A 60% Higher Write Speed, 4.2Gbps, 24-Channel 3D-Solid State Drive (SSD) with NAND Flash Channel Number Detector and Intelligent Program-Voltage Booster," IEEE Symposium on VLSI Circuits, Hawaii, pp. 233-234, 2010

#2010018

P.-H. Chen, K. Ishida, X. Zhang, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "0.18-V Input Charge Pump with Forward Body Biasing in Startup Circuit using 65nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp. 239-242, 2010

[Paper Link]

#2010019

Y. Okuma, K. Ishida, Y. Ryu, P.-H. Chen, K. Watanabe, M. Takamiya, and T. Sakurai, "0.5-V Input Digital LDO with 98.7% Current Efficiency and 2.7-uA Quiescent Current in 65nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp. 323-326, 2010

[Paper Link]

#2010020

N. Masunaga, K. Ishida, M. Takamiya, and T. Sakurai, "EMI Camera LSI (EMcam) with 12 x 4 On-Chip Loop Antenna Matrix in 65-nm CMOS to Measure EMI Noise Distribution with 60-um Spatial Precision," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp. 449-452, 2010

[Paper Link]

#2010021

T. Sekitani, K. Ishida, N. Masunaga, R. Takahashi, S. Shino, U. Zschieschang, H. Klauk, M. Takamiya, T. Sakurai, and T. Someya, "Organic CMOS Logic Papers with In-Field User Customizability," 2010 International Conference on Solid State Devices and Materials (SSDM), 2010

#2010022

M. Takamiya, K. Ishida, T. Sekitani, T. Someya, and T. Sakurai, "Design of Large Area Electronics with Organic Transistors," IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 500-503, 2010

[Paper Link]

#2010023

Y. Pu, X. Zhang, J. Huang, A. Muramatsu, M. Nomura, K. Hirairi, H. Takata, T. Sakurabayashi, S. Miyano, M. Takamiya, and T. Sakurai, "Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems," IEEE International Conference on Computer-Aided Design (ICCAD), San Jose, USA, pp. 625-631, 2010

[Paper Link]

#2010024

X. Zhang, Y. Pu, K. Ishida, Y. Ryu, Y. Okuma, P.-H. Chen, K. Watanabe, T. Sakurai, and M. Takamiya, "A 1-V Input, 0.2-V to 0.47-V Output Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction," IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, pp. 61-64, 2010

[Paper Link]

#2010025

L. Liu, T. Sakurai, and M. Takamiya, "0.6V Voltage Doubler and Clocked Comparator for Correlation-based Impulse Radio UWB Receiver in 65nm CMOS," IEEE Asian Solid-State Circuits Conference (A-SSCC), Beijing, China, pp. 301-304, 2010

[Paper Link]

#2010026

K. Ishida, K. Takemura, K. Baba, M. Takamiya, and T. Sakurai, "3D Stacked Buck Converter with 15um Thick Spiral Inductor on Silicon Interposer for Fine-Grain Power-Supply Voltage Control in SiP’s," IEEE International Conference on 3D System Integration (3D IC), Munich, Germany, 2010

#2010027

G.-S. Kim, K. Ikeuchi, M. Daito, M. Takamiya, and T. Sakurai, "A High-Speed, Low-Power Capacitive-Coupling Transceiver for Wireless Wafer-Level Testing Systems," IEEE International Conference on 3D System Integration (3D IC), Munich, Germany, 2010

#2010028

M. Takamiya, K. Ishida, T. Sekitani, U. Zschieschang, H. Klauk, T. Someya, and T. Sakurai, "Large Area Electronics with Organic Transistors and Novel Interconnects: EMI Measurement Sheet with Stretchable Interconnects and User Customizable Logic Paper (UCLP) with Ink-Jet Printed Interconnects," International Display Workshop (IDW), Fukuoka, Japan, pp. 1577-1580, 2010

[Paper Link]

#2010029

X. Zhang, K. Ishida, M. Takamiya, and T. Sakurai, "An On-Chip Characterizing System for Within-Die Delay Variation Measurement of Individual Standard Cells in 65-nm CMOS," Asia-South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 109-110, 2010

#2010030

P. -H. Chen, K. Ishida, K. Ikeuchi, X. Zhang, K. Honda, Y. Okuma, Y. Ryu, M. Takamiya, and T. Sakurai, "A 95mV-Startup Step-up Converter with VTH-Tuned Oscillator by Fixed-Charge Programming and Capacitor Pass-On Scheme," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 216-217, 2010

#2010031

K. Ishida, T. -C. Huang, K. Honda, T. Sekitani, H. Nakajima, H. Maeda, M. Takamiya, T. Someya, and T. Sakurai, "100-V AC Power Meter System-on-a-Film (SoF) Integrating 20-V Organic CMOS Digital and Analog Circuits with Floating Gate for Process Variation Compensation and 100-V Organic PMOS Rectifier," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, USA, pp. 218-219, 2010

L. Liu, T. Sakurai and M. Takamiya,"A 1.28mW 100Mb/s Impulse UWB Receiver with Charge-Domain Correlator and Embedded Sliding Scheme for Data Synchronization," Symp. on VLSI Circuits, Paper#14-3, June 2009

#2009002

K.Ishida, N.Masunaga, Z.Zhou, T.Yasufuku T.Sekitani, U.Zschieschang, H.Klauk, M.Takamiya, T.Someya, and T.Sakurai, "A Stretchable EMI Measurement Sheet with 8 x 8 Coil Array, 2V Organic CMOS Decoder and -70dBm EMI Detection Circuits in 0.18um CMOS," ISSCC 2009 digest of technical papers, paper#28.3, pp.472-473, Feb.2009

#2009003

T.Sakurai, "Wireless Power," ISSCC 2009 digest of technical papers, p.519, Feb.2009

#2009004

T.Sakurai, "Variability and Ultra-low Voltage Logic Design," ISSCC 2009 digest of technical papers, Forum 4 Ultra-Low-Voltage Circuit Design, p.507, Feb.2009

#2009005

K.Ishida, T.Yasufuku, S.Miyamoto, H.Nakai, M.Takamiya, T.Sakurai, K.Takeuchi, "A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD," ISSCC 2009 digest of thecnical papers, paper#13.2, pp.238-241, Feb.2009

#2009006

Y.Sugimori, Y.Kohama, M.Saito, Y.Yoshida, N.Miura, H.Ishikuro, T.Sakurai, T.Kuroda, "A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking," ISSCC 2009 digest of thecnical papers,paper#13.5, pp.244-245, Feb.2009

#2009007

T.Hatanaka, R.Yajima, S.Sakaki, M.Takahashi, Qiu-Hong Li, T.Horiuchi, S.Wang, Kwi-Young Yun, M.Takamiya, T.Sakurai, "Highly Scalable Fe(Ferroelectronics)-NAND Cell with MFIS (Metal-Ferroelectrric-Insulatore-Semiconductor) Structure for Sub-10 nm tera-Bit Capacity NAND Flash Memories," Proceedings of International Symposium on Secure-Life Electronics, pp.357-359, Jan.2009

#2009008

Y.Nakamura, D.Levacq, L.Xiao, T.Minakawa, T.Niiyama, M.Takamiya, T.Sakurai,"1/5 Power Reduction by Post-Fabrication Tuning with Fine-Grained Body Biasing," Proceedings of International Symposium on Secure-Life Electronics, pp.403-407, Jan.2009

#2009009

M.Takamiya, L.Liu, T.Sekitani, Y.Noguchi, S.Nakano, K.Zaitsu, T.Kuroda, T.Someya, T.Sakurai, "Ultra Low Power Inorgranic-Organic Hybrid Circuits and Digital-Analog Mixed Circuits for Secure Life," Proceedings of International Symposium on Secure-Life Electronics, pp.415-420, Jan.2009

#2009010

L.Liu, Y.Miyamoto, Z.Zhou, K.Sakaida, J.Ryu, K.Ishida, M.Takamiya, and T.Sakurai ,"A 100Mbps, 0.19mW Asynchronous Threshold Detector with DC Power-Free Pulse Discrimination for Impulse UWB Receiver," Asia-South Pacific Design Automation Conference (ASP-DAC) ,Jan.2009

#2009019

Y.Sugimori, Y.Kohama, M.Saito, Y.Yoshida, N.Miura, H.Ishikuro, T.Sakurai, T.Kuroda, "A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking," ISSCC'09, paper#13.5, pp.244-245, Feb.2009

#2009020

K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T.Sakurai, K. Takeuchi, "A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD," ISSCC'09, paper#13.2, pp.238-241, Feb.2009

#2009021

K. Ishida, N. Masunaga, Z. Zhou, T. Yasufuku, T. Sekitani, U.Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "A Stretchable EMI Measurement Sheet with 8 x 8 Coil Array, 2V Organic CMOS Decoder, and -70dBm EMI Detection Circuits in 0.18um CMOS," ISSCC'09, paper#28.3, pp.472-473, Feb.2009

#2009022

T. Sakurai, "Variability and Ultra-low Voltage Logic Design," ISSCC'09, Forum 4: Ultra-Low-Voltage Circuit Design, p.507, Feb. 2009

#2009023

T.Sakurai, "Wireless Power," ISSCC'09, Special Evening session 7: Next Generation Energy Scavenging Systems, p.519, Feb. 2009

#2009024

N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, and T. Kuroda, "A High-Speed Inductive-Coupling Link with Burst Transmission," IEEE Journal of Solid-State Circuits (JSSC), vol.44, no.3, pp.947-955, Mar. 2009

#2009025

G.-S. Kim, M. Takamiya, and T. Sakurai, "A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems," IEEE Transactions on Circuits and Systems-II: Express Briefs, Vol. 56, No. 9, pp. 709 - 713, Sep. 2009

#2009026

Takao Someya, Tsuyoshi Sekitani, Makoto Takamiya, Takayasu Sakurai, Ute Zschieschang and Hagen Klauk, "Printed organic transistors: Toward ambient electronics," Plenary talk, IEDM, Dec. 2009

#2009029

L. Liu, M. Takamiya, T. Sekitani, Y. Noguchi, S. Nakano, K. Zaitsu, T. Kuroda, T. Someya, and T. Sakurai, "A 107-pJ/bit 100-kb/s 0.18-um Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet," IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 56, No. 11, pp. 2511 - 2518, Nov. 2009

#2009031

Sanghoon Hwang, Hyunsik Im, Minkyu Song, Koichi Ishida, Toshiro Hiramoto, and Takayasu Sakurai, "Velocity Saturation Effects in a Short Channel Si- MOSFET and its Small Signal Characteristics," Journal of the Korean Physical Society, Vol.55, No.2, pp.581-584, Aug. 2009

#2009032

Y. Nakamura, M. Takamiya, and T. Sakurai, "An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise," IEICE Transaction on Electronics, E92-C, No.4, pp.468-472, Apr. 2009

#2009033

L. Liu, Y. Miyamoto, Z. Zhou, K. Sakaida, J. Ryu, K. Ishida, M. Takamiya, and T. Sakurai, "100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS," IEICE Transaction on Electronics, E92-C, No.6, pp.769-776, Jun. 2009

#2009034

T. Sekitani, K. Zaitsu, Y. Noguchi, K. Ishibe, M. Takamiya, T. Sakurai, and T. Someya, "Printed Nonvolatile Memory for a Sheet-Type Communication System," IEEE Transactions on Electron Devices, Vol. 56, No. 5, pp. 1027 - 1035, May 2009

#2009036

M. Daito, Y. Nakata, S. Sasaki, H. Gomyo, H. Kusamitsu, Y. Komoto, K. Iizuka, K. Ikeuchi, G. Kim, M. Takamiya, and T. Sakurai, "Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing," IEEE International Solid-State Circuits Conference (ISSCC), pp. 144-145, 2009

#2009037

T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K. Takeuchi, M. Takamiya, T. Sakurai, and T. Someya, "Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays," Science, Vol. 326, pp.1516-1519, 2009

#2009038

T. Someya, T. Sekitani, M. Takamiya, T. Sakurai, U. Zschieschang, and H. Klauk, "Printed Organic Transistors: Toward Ambient Electronics," IEEE International Electron Devices Meeting (IEDM), pp. 9-14, 2009

#2009039

Makoto Suzuki, Takuya Saraya, Ken Shimizu, Takayasu Sakurai, and Toshiro Hiramoto, "Improvement of Static Noise Margin in SRAM by Post-Fabrication Self-Convergence Technique," International Semiconductor Device Research Symposium (ISDRS), TP7-03, 2009

#2009040

G.-S. Kim, M. Takamiya, and T. Sakurai, "A Capacitive Coupling Interface with High Sensitivity for Wireless Wafer Testing," IEEE International Conference on 3D System Integration (3D IC), 2009

#2009041

T. Yasufuku, K. Ishida, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "Effect of Resistance of TSV’s on Performance of Boost Converter for Low Power 3D SSD with NAND Flash Memories," IEEE International Conference on 3D System Integration (3D IC) , 2009

#2009042

K. Ikeuchi, K. Sakaida, K. Ishida, T. Sakurai, and M. Takamiya, "Switched Resonant Clocking (SRC) Scheme Enabling Dynamic Frequency Scaling and Low-Speed Test," IEEE Custom Integrated Circuits Conference (CICC), pp. 33-36, 2009

#2009043

T. Yasufuku, K. Ishida, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai, and K. Takeuchi, "Inductor Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories," International Symposium on Low Power Electronics and Design (ISLPED), pp. 87-91, 2009

#2009044

N. Masunaga, K. Ishida, Z. Zhou, T. Yasufuku, T. Sekitani, M. Takamiya, T. Someya, and T. Sakurai, "A Flexible EMI Measurement Sheet to Measure Electric and Magnetic Fields Separately with Distributed Antennas and LSI’s," IEEE International Symposium on Electromagnetic Compatibility, pp. 156-160, 2009

#2009045

L. Liu, T. Sakurai, and M. Takamiya, "A 1.28mW 100Mb/s Impulse UWB Receiver with Charge-Domain Correlator and Embedded Sliding Scheme for Data Synchronization," IEEE Symposium on VLSI Circuits, pp. 146-147, 2009

#2009046

Makoto Suzuki, Takuya Saraya, Ken Shimizu, Takayasu Sakurai, and Toshiro Hiramoto, "Post-Fabrication Self-Convergence Scheme for Suppressing Variability in SRAM Cells and Logic Transistors," Symposium on VLSI Technology, pp.148-149, 2009

#2009047

T. Sakurai, "Next-Generation Power-Aware Integrated Circuit Design," International Meeting for Future of Electron Devices Kansai (IMFEDK), K-3, pp.18-21, 2009

#2009058

N. Miura, Y. Kohama, Y. Sugimori, H. Ishikuro, T. Sakurai, and T. Kuroda, "A High-Speed Inductive-Coupling Link with Burst Transmission," IEEE Journal of Solid-State Circuits (JSSC), vol.44, no.3, pp.947-955, Mar. 2009

#2009059

K. Ishida, N. Masunaga, Z. Zhou, T. Yasufuku, T. Sekitani, U. Zschieschang, H. Klauk, M. Takamiya, T. Someya, and T. Sakurai, "A Stretchable EMI Measurement Sheet with 8 x 8 Coil Array, 2V Organic CMOS Decoder, and -70dBm EMI Detection Circuits in 0.18um CMOS," ISSCC 2009 digest of technical papers, paper#28.3, pp.472-473, Feb. 2009

#2009060

K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T.Sakurai, K. Takeuchi, "A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD," ISSCC 2009 digest of thecnical papers, paper#13.2, pp.238-241, Feb. 2009

#2009061

Y.Sugimori, Y.Kohama, M.Saito, Y.Yoshida, N.Miura, H.Ishikuro, T.Sakurai, T.Kuroda, "A 2Gb/s 15pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking," ISSCC 2009 digest of thecnical papers, paper#13.5, pp.244-245, Feb. 2009

S.D.Choi, K. Ikeuchi, H.K.Kim, K.Inagaki, M. Takamiya, T.Sakurai,“Experimental Assessment of Logic Circuit Performance Variability with Regular Fabrics at 90nm Technology Node,”ESSCIRC, A2L-A1, Sept. 2008

#2008002

Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, and Takayasu Sakurai, "Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and Its Implications in Low Power DFM," Proc. 9th International Symposium on Quality Electronic Design, March, 2008

#2008003

L.Liu, M.Takamiya, T.Sekitani, Y.Noguchi, S.Nakano, K.Zaitsu, T.Kuroda, T.Someya, and T.Sakurai, "A 107pJ/bit 100kbps 0.18um Capacitive Coupling Transceiver with Asynchronous Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet," ISSCC'08, pp.292-293, Feb.2008

#2008004

N.Miura, Y.Kohama, Y.Sugimori, H.Ishikuro, T.Sakurai, and T.Kuroda, "An 11Gb/s Inductive-Coupling Link with Burst Transmission," ISSCC'08, pp.298-299, Feb.2008

#2008005

T. Niiyama, P. Zhe, K.Ishida, M. Murakata, M. Takamiya, and T. Sakurai, "Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and Its Implications in Low Power DFM," Proc. 9th International Symposium on Quality Electronic Design (ISQED), pp. 136-136, March, 2008

#2008006

T. Niiyama, P. Zhe, K. Ishida, M. Murakata, M. Takamiya, and T. Sakurai, “Increasing Minimum Operating Voltage (VDDmin) with Number of CMOS Logic Gates and Experimental Verification with up to 1Mega-Stage Ring Oscillators," ISLPED'08, pp.117-122, Aug. 2008

#2008007

L.Liu, Y.Miyamoto, Z.Zhou, K.Sakaida, R.Jisun, K.Ishida, M.Takamiya and T.Sakurai, "A 100Mbps, 0.41mW, DC-960MHz Band Impulse UWB Transceiver in 90nm CMOS," Symp. on VLSI Circuits, June 2008

#2008008

Y.Nakamura, D.Levacq, L.Xiao, T.Minakawa, T.Niiyama, M.Takamiya, and T.Sakurai, "1/5 Power Reduction by Global Optimization based on Fine-Grained Body Biasing," CICC'08, pp. 547-550, Sept. 2008

#2008009

K.Ikeuchi, K.Inagaki, H.Kusamitsu, T.Ito, M.Takamiya, and T.Sakurai, "500Mbps, 670uW/pin Capacitively Coupled Receiver with Self Reset Scheme for Wireless Connectors," A-SSCC'08, pp.93-96, Nov. 2008

#2008010

T.Sakurai, "Next-Generation Power-Aware Design (Plenary Talk)", ISLPED08, Aug. 13, Bangalore, India.

#2008011

T.Sakurai, "Solving Issues of Integrated Circuits by 3D-Stacking Meeting with the Era of Power, Integrity Attackers and NRE Explosion and a Bit of Future (Pleanary Talk)," ESSCIRC, B4L-A1, Sept. 2008

#2008012

M.Takamiya, T.Sekitani, Y.Miyamoto, Y.Noguchi, H.Kawaguchi, T.Someya, T.Sakurai, "Design of Wireless Power Transmission Sheet with Organic FETs and Plastic MEMS Switches," Proceedings of International Symposium on Secure-Life Electronics, pp.557-561, Mar.2008

#2008013

K.Onizuka, M.Takamiya, T.Sakurai,"Recent Progress in On-Chip Power Supply Circuits," Proceedings of International Symposium on Secure-Life Electronics, pp.563-569, Mar.2008

#2008014

T.Niiyama, K.Ishida, M.Takamiya, T.Sakurai,"Expected Vectorless Teacher-Student Swap(TSS) Test method with Dual Power Supply Voltages for 0.3V Homogeneous Multi-core LSI's," IEEE 2008 Custom Inegrated Circuits Conference, Paper#8.5, pp.137-140, Sept.2008

#2008015

T.Sakurai, "Solving Issues of LSI by 3-Dimensional System-in-Package (Plenary talk)," International Conference on Electronics Packaging, Jan.2008

#2008016

T.Someya, T.Sekitani, M.Takamiya, T.Sakurai ,"Recent Progress of Wireless Transmission Systems Using Printed Plastic MEMS Switches and Organic Transistors," Eighth International Workshop on Micro and Nanotechnology for Power Generation and Energy Conversion Applications (PowerMEMS + microEMS 2008), Nov.2008

#2008017

Y.Kato, T.Sekitani, Y.Noguchi, M.Takamiya, T.Sakurai, T. Someya ,"A large-area, flexible, ultrasonic imaging system with a printed organic transistor active matrix," IEEE International Electron Devices Meeting (IEDM) ,Paper#4.7, Dec.2008

#2008018

N.Miura, Y.Kohama, Y.Sugimori, H.Ishikuro, T.Sakurai, and T.Kuroda, "An 11Gb/s Inductive-Coupling Link with Burst Transmission," ISSCC'08 digest of technical papers, pp.298-299, Feb.2008

#2008019

N.Miura, H.Ishikuro, K.Niitsu, T.Sakurai, and T.Kuroda, "A 0.14pJ/b Inductive-Coupling Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE Journal of Solid-State Circuits (JSSC), vol.43, no.1, pp.285-291, Jan. 2008

#2008020

T.Sakurai, "Next-Generation Power-Aware Design (Plenary Talk)," ISLPED'08, Bangalore, India, Aug.2008

#2008021

T.Sakurai, "Variability and Ultra-low Voltage Logic Design," ISSCC 2009 digest of technical papers, Forum 4 Ultra-Low-Voltage Circuit Design, p.507, Feb.2008

#2008032

Y.Kato, T.Sekitani, Y.Noguchi, M.Takamiya, T.Sakurai, T. Someya, "A large-area, flexible, ultrasonic imaging system with a printed organic transistor active matrix," IEEE International Electron Devices Meeting (IEDM), #4.7, Dec. 2008

#2008033

N. Miura, H. Ishikuro, K. Niitsu, T. Sakurai, and T. Kuroda, "A 0.14pJ/b Inductive-Coupling Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE Journal of Solid-State Circuits (JSSC), vol.43, no.1, pp.285-291, Jan. 2008

Takayasu Sakurai, "Meeting with the Forthcoming IC Design - The Era of Power, Variability and NRE Explosion and a Bit of the Future," Asia and South Pacific Design Automation Conference, pp.viii, Jan. 2007

#2007002

Takayasu Sakurai, "Advances in Low-Power Integrated Circuits and Large-Area Electronics for Ubiquitous Electrinics-Solving Issues with 3D-Stacking-," Proceedings of COE Sympoium on Advanced Electtrinics for Future Generations, 1, pp.89-94, Jan. 2007

#2007003

M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display," IEEE Journal of Solid-State Circuits, Vol.42, No.1, pp.93-100, Jan. 2007

#2007004

N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "A 1 Tb/s 3W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link," IEEE Journal of Solid-State Circuits, Vol.42, No.1, pp.111-122, Jan. 2007

#2007005

Takayasu Sakurai, "Organic-Transistor Circuit Design," IEEE International Solid-State Circuits Conference , U.S.A., T8, Feb. 11, 2007

#2007006

M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, and T. Sakurai, "Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches," IEEE International Solid-State Circuits Conference, pp.362-609, Feb. 2007

#2007007

N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," IEEE International Solid-State Circuits Conference, pp.358-608, Feb. 2007

#2007008

Y. Kato, T. Sekitani, M. Takamiya, M. Doi, K. Asaka, T. Sakurai, and T. Someya, "Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators," IEEE Transactions on Electron Devices, Vol.54, No.2, pp.202-209, Feb. 2007

#2007009

N. Miura, T. Sakurai, and T. Kuroda, "Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array," IEEE Journal of Solid-State Circuits, Vol.42, No.2, pp.410-421, Feb. 2007

#2007014

Takayasu Sakurai, "Sloving issues of VLSI by 3D-SiP-From design perspective," Technical Digest of the International 3D System Integration Conference, Tokyo, 14, Mar. 27, 2007

#2007015

Kazuki Hizu, Tsuyoshi Sekitani, Joe Otsuki, Makoto Takamiya, Takayasu Sakurai, and Takao Someya, "Air-stable operation of organic complementary circuits on a polyimide film," The Fourth International Conference on Molecular Electronics and Bioelectronics (M&BE4), Mar. 2007

#2007016

Y. Kato, T. Sekitani, M. Takamiya, M. Doi, K. Asaka, T. Sakurai, and T. Someya, "Integration of organic semiconducting nano-materials and polymer actuators and their application," 2007 Frontiers in Nanoscale Science and Technology, Tokyo, A15, Mar. 2007

#2007022

S. Nakano, T. Sekitani, S. Takatani, M. Takamiya, T. Sakurai, and T. Someya, "Printed Plastic Switch Array for the Application to High Power Electronics," Material Research Society (MRS) Spring Meeting, San Francisco, USA, N8.9, Apr. 2007

#2007023

T. Someya, T. Sekitani, Y. Noguchi, S. Nakano, S. Takatani, M. Takamiya, and T. Sakurai, "Printed Organic Transistors for Large-area Sensors and Actuators," Material Research Society (MRS) Spring Meeting, San Francisco, USA, O10.6, Apr. 2007

#2007024

Fayez Robert Saliba, Hiroshi Kawaguchi, and Takayasu Sakurai, "A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's," IEICE Transactions on Electronics, Vol.Vol.E90-C, No.4, pp.743-748, Apr. 2007

#2007025

Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, and Takayasu Sakurai, "An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors," IEICE Transactions on Electronics, Vol.Vol.E90-C, No.4, pp.786-792, Apr. 2007

#2007026

Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, and Tadahiro Kuroda, "Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link," IEICE Transactions on Electronics, Vol.Vol.E90-C, No.4, pp.829-835, Apr. 2007

#2007027

Tsuyoshi Sekitani, Makoto Takamiya, Yoshiaki Noguchi, Shintaro Nakano, Yusaku Kato, Takayasu Sakurai, and Takao Someya, "A large-area wireless power-transmission sheet using printed organic transistors and plastic MEMS switches," Nature Materials, Vol.6, No., pp.413-417, Apr. 2007

#2007028

Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, and Takayasu Sakurai, "Design for Mixed Circuits of Organic FETs and Plastic MEMS Switches for Wireless Power Transmission Sheet," IEEE International Conference on Integrated Circuit Design and Technology, pp.168-171, June 1, 2007

#2007029

Kohei Onizuka, Makoto Takamiya, Hiroshi Kawaguchi, and Takayasu Sakurai, "A design methodology of chip-to-chip wireless power transmission system," IEEE International Conference on Integrated Circuit Design and Technology, pp.143-146, June 1, 2007

#2007030

Yasumi Nakamura, Makoto Takamiya, and Takayasu Sakurai, "An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise," IEEE Symposium on VLSI Circuits, pp.124-125, June 2007

#2007031

Takao Someya, Takayasu Sakurai, Tsuyoshi Sekitani, and Yoshiaki Noguchi, "Printed Organic Transistors for Large-Area Electronics," 6th International Conference on Polymers and Adhesives in Microelectronics and Photonics, pp.6-11, June 2007

#2007032

Tsuyoshi Sekitani, Makoto Takamiya, Shintaro Nakano, Yoshiaki Noguchi, Yusaku Kato, Takayasu Sakurai, and Takao Someya, "Printed organic transistor circuits for a large-area wireless power transmission sheet," 3rd Annual Organic Microelectronics Workshop, Seattle, USA, July 2007

#2007041

Takayasu Sakurai, "(Invited)Meeting with the Forthcoming IC Design-Solving issues by 3D stacking," SBCCI2007, Rio de Janeiro, Bragil, pp.2, Sep. 2007

#2007042

D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution," 33rd European Solid-State Circuits Conference (ESSCIRC), Munich, Germany, pp.190-193, Sep. 2007

#2007043

D. Levacq, T. Minakawa, M. Takamiya, and T. Sakurai, "A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 x 1 Transistor Arrays in 90nm CMOS," IEEE Custom Integrated Circuits Conference (CICC), San Jose, USA, pp.257-260, Sep. 2007

#2007048

D. Levacq, M. Takamiya, and T. Sakurai, "Backgate Bias Accelerator for 10ns-order Sleep-to-Active Modes Transition Time," IEEE Asian Solid-State Circuits Conference (A-SSCC), Jeju, Korea, pp.296-299, Nov. 2007

#2007049

K. Onizuka, K. Inagaki, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs," IEEE Journal of Solid-State Circuits, Vol.42, No.11, pp.2404-2410, Nov. 2007

#2007050

Hiroshi Kawaguchi, Danardono Dwi Antono, and Takayasu Sakurai, "Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines," IEICE Transactions on Electronics, Vol.Vol.E90-A, No.12, pp.2669-2681, Nov. 2007

#2007051

M. Takamiya, T. Sekitani, Y. Miyamoto, Y. Noguchi, H. Kawaguchi, T. Someya, and T. Sakurai, "(Invited) Wireless Power Transmission Sheet with Organic FETs and Plastic MEMS Switches," International Display Workshop (IDW), Sapporo, Japan, pp.95-98, Dec. 2007

#2007052

T. Sekitani, Y. Noguchi, S. Nakano, K. Zaitsu, Y. Kato, M. Takamiya, T. Sakurai, and T. Someya, "Communication Sheets Using Printed Organic Nonvolatile Memories," IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, Dec. 2007

T. Someya, T. Sekitani, and T. Sakurai, "Organic TFT-AM for Large-Area Sensors and Actuators," 2006 International Thin-Film Transistor Conference, Session 6: Emerging Technology, Kitakyushu, 6.1, Jan. 19, 2006

#2006003

N. Miura, D. Mizoguchi, M. Inoue, T. Sakurai, and T. Kuroda, "A 195-Gb/s 1.2-W Inductive Inter-Chip Wireless Superconnect for 3-D-Stacked System in a Package," IEEE Journal of Solid-State Circuits (JSSC), Vol.41, No.1, pp.23-34, Jan. 2006

#2006004

S. Iba, Y. Kato, T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Use of laser drilling in the manufacture of organic inverter circuits," Analytical and Bioanalytical Chemistry, Vol.384, No.2, pp.374-377, Jan. 2006

#2006008

K. Ishida, A. Tamtrakarn, and T. Sakurai, "A 0.5-V Sigma-Delta Modulator Using Analog T-Switch Scheme for the Subthreshold Leakage Suppression," 2006 IEEE Asia and South Pacific Design Automation Conference, pp.98-99, Jan. 2006 (PDF)(PDF2)

#2006011

N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "A 1Tb/s 3W Inductive-Coupling Transceiver for Inter-Chip Clock and Data Link," IEEE International Solid-State Circuits Conference (ISSCC'06), pp.424-425, Feb. 2006

#2006013

M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase the Static Noise Margin," IEEE International Solid-State Circuits Conference (ISSCC'06), pp.276-277, Feb. 2006

#2006014

Y. Kato, T. Sekitani, M. Takamiya, Masao Doi, K. Asaka, T. Sakurai, and T. Someya, "Sheet-Type Braille Displays by Integrating Organic Field-Effect Transistors and Polymeric Actuators," IEEE Transactions on Electron Devices, Vol.54, No.2, pp.202-209, Feb. 2007

#2006019

C. Q. Tran, H. Kawaguchi, and T. Sakurai, "Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating Dual-VTH/VDD and Micro-VDD-Hopping," IEICE Transactions on Electronics, Vol.E89-C, No.3, pp.280-286, Mar. 2006

#2006020

D. D. Antono, K. Inagaki, H. Kawaguchi, and T. Sakurai, "Trends of On-Chip Interconnects in Deep Sub-Micron ," IEICE Transactions on Electronics, Vol.E89-C, No.3, pp.392-394, Mar. 2006 (PDF)

#2006025

T. Someya, T. Sakurai, and T. Sekitani, "Future Prospects of Flexible, Large-Area Sensors and Actuators with Organic Transistor ICs," 2006 VLSI-TSA conference, Taiwan, Apr. 24, 2006

#2006026

T. Someya, Y. Noguchi, Y. Kato, T. Sekitani, and T. Sakurai, "Printed organic transistors for large-area, flexible sensors and actuators," Material Research Society (MRS) Spring Meeting, Symposium L: Materials for Next-Generation Display Systems, San Francisco, Apr. 2006

#2006027

T. Someya, T. Sekitani, and T. Sakurai, "Conformable electronic artificial skins with organic transistor integrated circuits," Material Research Society (MRS) Spring Meeting, Symposium CC: Electrobiological Interfaces on Soft Substrates, San Francisco, Apr. 2006

#2006028

K. Hizu, T. Sekitani, Y. Shimada, J. Otsuki, M. Takamiya, T. Sakurai, and T. Someya, "Low voltage operation of organic CMOS inverter circuit with double-gate structure," Material Research Society (MRS) Spring Meeting, Symposium M: Conjugated Organic Materials - Synthesis, Structure, Device and Applications, San Francisco, Apr. 2006

#2006029

T. Sekitani, Y. Takamatsu, S. Nakano, T. Sakurai, and T. Someya, "Hall effect measurements using pentacene thin-film transistors on plastic films," Material Research Society (MRS) Spring Meeting, Symposium M: Conjugated Organic Materials - Synthesis, Structure, Device and Applications, San Francisco, Apr. 2006

#2006030

T. Sekitani, T. Someya, and T. Sakurai, "Effects of Annealing on Pentacene Field-Effect Transistors using Polyimide Gate Dielectric Layers," Journal of Applied Physics, Vol.100, 024513, No., Apr. 2006

#2006031

K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai, "Managing Subthreshold Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by Analog T- Switch (AT-Switch) and Super Cut-off CMOS," IEEE Journal of Solid-State Circuits (JSSC), Vol.41, No.4, pp.859-867, Apr. 2006 (PDF)

#2006032

K. S. Min, H. D. Choi, H. Y. Choi, H. kawaguchi, and T. Sakurai, "Leakage-Suppressed Clock-Gating Circuit with Zigzag Super Cut-Off CMOS (ZSCCMOS) for Leakage-Dominant Sub70-nm and Sub-1-V-VDD LSIs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.14, No.4, pp.430-435, Apr. 2006

#2006035

T. Someya, T. Sekitani, and T. Sakurai, "Printed organic transistors for large-area electronics," The 6th International Meeting on Information Display and the International Display Manufacturing Conference (IMID/IDMC 2006), Display Electronics & System, Exhibition & Convention Center (EXCO) in Daegu, Korea, May 8, 2006

#2006036

T. Someya, T. Sekitani, and T. Sakurai, "Conformable, lightweight, large-area sheet-type sensors with organic transistor integrated circuits," Symposium Q: Chem & Bio Sensing Transistors: from Materials to Systems, The European Materials Research Society (E-MRS 2006) Spring Meeting, Acropolis Congress Center, Nice, France, May 2006

#2006038

M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai, "Low Power and Flexible Braille Sheet Display with Organic FET's and Plastic Actuators," IEEE International Conference on IC Design and Technology (ICICDT), Padova, Italy, pp.219-222, May 2006

#2006039

T. Someya, T. Sakurai, and T. Sekitani, "Recent progress of organic TFT active matrices for large-area electronics applications," International Congress of Imaging Science: ICIS'06, Rochester, New York, May 2006

#2006045

M. Inoue, N. Miura, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "Daisy Chain for Power Reduction in Inductive-Coupling CMOS Link," IEEE Symposium on VLSI Circuits, 8.3, pp.80-81, June 15, 2006 (PDF)

#2006046

K. Inagaki, D. Antono, M. Takamiya, S. Kumashiro, and T. Sakurai, "A 1-ps Resolution On-chip Sampling Oscilloscope with 64:1 Tunable Sampling Range Based on Ramp Waveform Division Scheme," IEEE Symposium on VLSI Circuits, 8.1, pp.76-77, June 15, 2006 (PDF)

#2006047

T. Sekitani, Shingo Iba, Y. Kato, Y. Noguchi, T. Sakurai, and T. Someya, "Submillimeter radius bendable organic field-effect transistors," JOURNAL OF NON-CRYSTALLINE SOLIDS, Vol.352, No., pp.1769-1773, June 15, 2006

#2006048

A. Tamtrakarn, H. Ishikuro, K. Ishida, M. Takamiya, and T. Sakurai, "A 1-V 299ƒÊW Flashing UWB Transceiver Based on Double Thresholding Scheme," IEEE Symposium on VLSI Circuits, 23.2, pp.250-251, June 17, 2006

#2006049

T. Someya, T. Sakurai, and T. Sekitani, "Large-area Electronics Based on Organic Transistors," 64th Device Research Conference (DRC), Penn State University, June 28, 2006

#2006051

T. Sekitani, Y. Takamatsu, S. Nakano, T. Sakurai, and T. Someya, "Hall effect measurements using polycrystalline pentacene field-effect transistors on plastic films," Applied Physics Letters, Vol.88(25), No.Art. No. 253508, June 2006

#2006054

T. Someya, T. Sakurai, and T. Sekitani, "Flexible, Large-Area Sensors and Actuators using Organic Transistor Integrated Circuits," 2006 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices (AWAD2006), Tohoku University, July 3, 2006

#2006055

T. Someya, T. Sakurai, and T. Sekitani, "Large-area Electronics Based on Organic Transistor ICs," 2nd Annual Organic Microelectronics Workshop, Tronto, July 9, 2006

#2006056

N. Miura, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, and T. Kuroda, "A 1Tb/s 3W Inductive-Coupling Transceiver for 3D ICs," 2006 Intenational PhD Workshop on SoC (IPS), July 2006

#2006058

T. Sekitani, Y. Noguchi, T. Sakurai, and T. Someya, "Inkjet Printing of 33 cm Organic Field-Effect Transistor Active Matrices for the Application to Electronic Artificial Skins," 2006 The International Conference on Science and Technology of Synthetic Metals (ICSM2006), Trinity College Dublin in Ireland, July 2006

#2006059

T. Someya, T. Sakurai, and T. Sekitani , "Flexible, Large-Area Electronics Using Organic Transistors," 25th Electronic Materials Symposium, Session G: Organic Electronics, July 2006

#2006069

Y. Takamatsu, T. Sekitani, S. Nakano, T. Sakurai, and T. Someya, "Hall effect of polycrystalline pentacene field-effect transistors on plastic films," International Conference on Solid State Devices and Materials (SSDM), Organic Materials Science, Device Physics and Applications, Yokohama, Sep. 11, 2006

#2006071

Atit Tamtrakarn, Hiroki Ishikuro, Koichi Ishida, and Takayasu Sakurai , "Compact outside-rail circuit structure by single-cascode two-transistor topology ," IEEE Custom Integrated Circuits Conference (CICC), pp.619-622, Sep. 2006

#2006072

K. Onizuka, H. Kawaguchi, M. Takamiya, T. Kuroda, and T. Sakurai, "Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications," IEEE Custom Integrated Circuits Conference, 15.1, pp.575-578, Sep. 2006 (PDF)

#2006077

T. Sekitani, Y. Takamatsu, T. Sakurai, and T. Someya, "Strain and Hall Effects of Pentacence TFTs on Plastic Films," KINKEN Workshop on Organic Field Effect Transistor, Institute for Materials Research, Oct. 2006

#2006078

Y. Noguchi, T. Sekitani, T. Sakurai, and T. Someya, "ROBOT SKINS USING INKJETTED ORGANIC TRANSISTOR ACTIVE MATRICES," Korea-Japan Joint Forum (KJF) 2006 -Organic Materials for Electronics and Photonics-, Organic Display and Transistors, TOKI MESSE, Niigata Convention Center, Oct. 2006

#2006079

T. Someya, T. Sakurai, and T. Sekitani, "Recent Progress of Flexible, Large-area Sensors and Actuators with Organic Transistor Integrated Circuits," KINKEN Workshop on Organic Field Effect Transistor, Institute for Materials Research , Oct. 2006

#2006080

H. Kawaguchi, S. Iba, Y. Kato, T. Sekitani, T. Someya, and T. Sakurai, "A 3D-Stack Organic Sheet-Type Scanner with Double-Wordline and Double-Bitline Structure," IEEE Sensors Journal, Vol.6, No.5, pp.1209-1217, Oct. 2006

#2006082

T. Sekitani and T. Someya, "Air-stable operation of pentacene field-effect transistors on plastic films using organic/metal hybrid passivation layers," The 2006 International Symposium on Flexible Electronics and Display (ISFED), Taiwan, Nov. 2006

#2006083

K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "VDD-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time," IEEE Journal of Solid-State Circuits, Vol.41, No.11, pp.2382-2389, Nov. 2006 (PDF)

#2006084

T. Sakurai and M. Ikeda, "Introduction to the Special Issue on the 2005 Asian Solid-State Circuits Conference(A-SSCC'05)," IEEE Journal of Solid-State Circuits, Vol.41, No.11, pp.2364-2365, Nov. 2006

#2006085

K. Onizuka, H. Kawaguchi, M. Takamiya, and T. Sakurai, "Stacked-chip Implementation of On-Chip Buck Converter for Power-Aware Distributed Power Supply Systems," IEEE Asian Solid-State Circuits Conference, pp.127-130, Nov. 2006 (PDF)

#2006098

M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and T. Sakurai. , "Flexible Braille Sheet Display with Organic FETs and Plastic Actuators," International Display Workshop (IDW), Otsu, Dec. 8, 2006

#2006100

T. Sekitani, M. Takamiya, Y. Noguchi, S. Nakano, Y. Kato, K. Hizu, H. Kawaguchi, T. Sakurai, and T. Someya, "A Large-Area Flexible Wireless Power Transmission Sheet Using Printed Plastic MEMS Switches and Organic Field-Effect Transistors," 2006 IEEE International Electron Devices Meeting (IEDM2006), San Francisco, Dec. 2006

#2006107

T. Someya, T. Sekitani, S. Iba, Y. Kato, T. Sakurai, and H. Kawaguchi, "Organic transistor integrated circuits for large-area sensors," MOLECULAR CRYSTALS AND LIQUID CRYSTALS, Vol., No., pp.13-22, 2006

#2006108

Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, and Takayasu Sakurai, "Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's ," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E89-A, No.12, pp.3569-3578 , 2006 (PDF)

H. Kawaguchi, T. Someya, T. Sekitani, and T. Sakurai, "Cut-and-Paste Customization of Organic FET Integrated Circuit and Its Application to Electronic Artificial Skin," IEEE Journal of Solid State Circuits, pp.177-185, Jan. 2005 (PDF)

#2005009

T. Sekitani, Y. Kato, S. Iba, H. Shinaoka, T. Someya, T. Sakurai, and S. Takagi, "Bending experiment on pentacene field-effect transistors on plastic films," Applied Physics Letters vol. , 86, pp.073511, Feb. 14, 2005

#2005013

H. Kawaguchi, Y. Shin, and T. Sakurai, "ƒÊITRON-LP: Power-Conscious Real-Time OS Based on Cooperative Voltage Scaling for Multimedia Applications," IEEE Transaction on Multimedia, 7, pp.67-74, Feb. 2005 (PDF)

#2005033

T. Sakurai, "How can we achieve Low-Power and High-Performance?," 2005 IEEE Internatiional Confernce on Integrated Circuit and Technology, pp.112, May 10, 2005

#2005034

Canh Quang Tran, H. Kawaguchi, and T, Sakurai, "Low-power High-speed Level Shifter Design for Block-level Dynamic Voltage Scaling Environment," IEEE International Conference on Integrated Circuit Design and Technology, Texas, USA, 1, pp.229-232, May 11, 2005 (PDF)

#2005037

Canh Quang Tran, H. Kawaguchi, and T, Sakurai, "More Than Two orders of Magnitude Leakage Current Reduction in Look-Up Table for FPGA's," IEEE International Symposium on Circuits and Systems, pp.4701-4704, May 2005 (PDF)

#2005039

T. Someya, T. Sekitani, H. Kawaguchi, S. Iba, and Y. Kato, "Recent Advances in Applications of Organic Inergrated Circuits for Large-Area Electronics," 2005 IEEE Internatiional Confernce on Integrated Circuit and Technology, pp.57-62, May 2005

#2005045

Kyu-won Choi, Yingxue Xu, and T. Sakurai, "Optimal zigzag (OZ): an effective yet feasible power-gating scheme achieving two orders of magnitude lower standby leakage," IEEE Symposium on VLSI Circuits, pp.312-315, June 2005

#2005046

F.R. Saliba, H. Kawaguchi, and T. Sakurai, "Experimental verification of row-by-row variable VDD scheme reducing 95% active leakage power of SRAMs," IEEE Symposium on VLSI Circuits, pp.162-165, June 2005

#2005050

T. Someya, Y. Kato, T. Sekitani, S. Iba, Y. Noguchi, Y. Murase, H. Kawaguchi, and T. Sakurai, "Conformable, flexible, large-area networks of pressure and thermal sensors with organic transistor active matrixes," Proceedings of the National Academy of Sciences of the United States of America, , 102, Issue 35, pp.12321-12325, Aug. 30, 2005 (PDF)

#2005051

N. Miura, D. Mizoguchi, T. Sakurai, and T. Kuroda, "Analysis and Design of Inductive Coupling and Transceiver Circuit for Inductive Inter-Chip Wireless Superconnect," IEEE Journal of Solid-State Circuits (JSSC), 40, 4, pp.pp. 829-837, Aug. 2005 (PDF)

#2005061

T. Someya, T. Sekitani, Shi. Iba, Y. Kato, Y. Noguchi, K. Hizu, and T. Sakurai, "(Invited) Conformable electronic artificial skins with organic transistor integrated circuits," Korea-Japan Joint Forum(KJF) 2005 on Organic Materials for Electronics, Daejeon, Korea, Oct. 26-29, 2005

#2005062

K. Onizuka and T. Sakurai, "VDD-Hopping Accelerator for On-Chip Power Supplies Achieving Nano-Second Order Transient Time," IEEE Asian Solid-State Circuits Conference, Hsinchu, Taiwan, Session6-1, pp.145-148, Nov. 2, 2005 (PDF)

#2005063

Canh Quang Tran, H. Kawaguchi, and T, Sakurai, "95% Leakage-Reduced FPGA using Zigzag Power-gating, Dual-VTH/VDD and Micro-VDD-Hopping," IEEE Asian Solid-State Circuits Conference, Hsinchu, Taiwan, 6, pp.149-152, Nov. 2, 2005 (PDF)

#2005065

S. Iba, Y. Kato, T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Use of laser drilling in the manufacture of organic inverter circuits," Analytical and Bioanalytical Chemistry, 384, pp.374 - 377, Nov. 11, 2005

#2005066

Kyu-won Choi, Y. Xu, K. Inagaki, and T. Sakurai, "Optimal zigzag scheme achieving lower standby leakage," International Symposium on Quantum Dots and Nanoelectronics, Tokyo Garden Place, Nov. 18, 2005

#2005068

T. Someya, Y. Kato, S. Iba, Y. Noguchi, T. Sekitani, H. Kawaguchi, and T. Sakurai , "Integration of organic FETs With Organic Photodiodes for a Large Area, Flwxible, and Lightweight Sheet Image Scanners," IEEE Transactions on Electron Devices, 52, 11, pp.2502-2511, Nov. 2005 (PDF)

#2005074

T. Sekitani, S. Iba, Y. Kato, Y. Noguchi, T. Someya, and T. Sakura, "Ultra-flexible organic field-effect transistors embedded at a neutral strain position," Applied Physics Letters 87, pp.173502, 2005 (PDF)

#2005075

T. Sekitani, S. Iba, T. Sekitani, Y. Kato, T. Someya, and T. Sakurai, "Suppression of DC bias stress-induced degradation of organic field-effect transistors using postannealing effects ," Applied Physics Letters 87, pp.073505 , 2005 (PDF)

#2005076

S. Iba, T. Sekitani, Y. Kato, T. Someya, H. Kawaguchi, M. Takamiya, T. Sakurai, and S. Takagi, "Control of threshold voltage of organic field-effect transistors with double-gate structures," Applied Physics Letters 87, pp.023509 ., 2005 (PDF)

#2005077

T. Sekitani, Y. Kato, S. Iba, and T. Someya, "Bending Effect of Organic Field-Effect Trasistors with Polyimide Gate Dielectric Layers," Japanese Journal of Applied Physics, 44, pp.2841-2844, 2005 (PDF)

T. Sakurai, "Adaptive Circuit Techniques for Managing Variations," IEEE International Solid-State Circuits Conference Digest of Technical Papers, U.S.A., Feb. 19, 2004 (PDF)

#2004008

T. Someya, H. Kawaguchi, and T. Sakurai, "Cut-and-Paste Organic FET Customized ICs for Application to Artificial Skin," IEEE International Solid-State Circuits Conference Digest of Technical Papers, U.S.A., Feb. 2004 (PDF)

#2004009

D. Mizoguchi, Y. Yusof, N. Miura, T. Sakurai, T. Kuroda, "A 1.2Gb/s/pin Wireless Superconnect Based on Inductive Inter-Chip Signaling," IEEE International Symposium on Quality Electronic Design, U.S.A., Session7-6, Feb. 2004 (PDF)

#2004010

T. Sakurai, "Perspectives in Power-Aware and Large-Area Integrated Circuits for Ubiquitous Electronics," International Symposium on Electronics for Future Generations, Tokyo, pp.71-74, Mar. 10, 2004 (PDF)

#2004011

T. Someya and T. Sakurai, "Flexible, Large-Area sensor Matrix with Organic Taransistor-Based Circuits," 3rd International Symposium on Organic Molecular Electronics (ISOME2004) , Kyoto, Mar. 18, 2004 (PDF)

#2004017

T. Sakurai, "Perspective of Power-Aware Electronics," IEEE Distinguished Lecturer Program in Taiwan, Taiwan, Mar. 2004

#2004025

T. Sekitani, H. Kawaguchi, T. Sakurai, and T. Someya, "Organic field-effect transistors with bending radius down to 1 mm," 2004 Materials Research Society (MRS) Spring Meeting, USA(SF), Apr. 2004 (PDF)

#2004026

H. Kawaguchi, T. Someya, T. Sekitani, and T. Sakurai, "Cut-and-Paste Customization of Organic FET Integrated Circuit and Its Application to Electronic Artificial Skin," IEEE Journal of Solid State Circuits, Vol., No., Apr. 2004 (PDF)

#2004027

T. Sakurai, "Perspectives of Low-Power VLSI's," IEICE Transactions on Electronics, E87-C, 4, pp.429-437, Apr. 2004 (PDF)

#2004029

T.Sakurai, "Perspectives of Low Power Electronics ," 2004 Internasional Confernce on Integrated Circuit Design and Technology, Austin, Texas, pp.1-147, May 17, 2004

#2004037

H. Kawaguchi, Y. Shin, and T. Sakurai, "ƒÊITRON-LP: Power-Conscious Real-Time OS Based on Cooperative Voltage Scaling for Multimedia Applications," IEEE Transaction on Multimedia, Vol., No., 2004 (PDF)

#2004040

K. Kanda, S. Hattori, and T. Sakurai, "90% write power-saving SRAM using sense-amplifying memory cell," IEEE J. Solid-State Circuits, Vol.39, No.6, pp.927-933, Jan. 2004 (PDF)

#2004043

T. Sakurai, "Low Power Digital Circuit Design," European Solid-State Circuits Conference, Leuven, Belgium, Sep. 21-23, 2004 (PDF)

#2004059

Jin-Hyeok Choi, Yingxue Xu, Takayasu Sakurai, "Statistical Leakage Current Reduction in High-Leakage Environments Using Locality of Block Activation in Time Domain," IEEE Journal of Solid-State Circuits, Vol.Vol.37, No.No.9, pp.pp.1497-1503, Sep. 2004 (PDF)

#2004063

T. Miyazaki, T. Q. Canh, H. Kawaguchi, and T. Sakurai, "Observation of one-fifth-a-clock wake-up time of power-gated circuit," Proceedings of IEEE Custom Integrated Circuits Conference, pp.pp. 87-90, Oct. 2004 (PDF)

#2004065

T. Someya, T. Sakurai, T. Sekitani, H. Kawaguchi, S. Iba, and Y. Kato," , , . 2004., "A Large-Area, Flexible, and Lightweight Sheet Image Scanner," IEEE International Electron Devices Meeting Digest of Technical Papers, #15.1, Dec. 2004

#2004066

T. Sakurai, "Perspectives of Low Power Electronics," 2004 IEEE International Confernce on Semiconductor Electronics, Kuala Lumpur, ‡VB(Parameswara ‡U, level2), Dec. 2004

H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, and T. Sakurai, "A 0.5-V, 400-MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.106-107, Feb. 2003 (PDF)

#2003004

K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.186-187, Feb. 2003 (PDF)

#2003005

K. Min, H. Kawaguchi, T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.400-401, Feb. 2003 (PDF)

#2003010

S. Misaka, K. Toyama, T. Aritsuka, K. Uchiyama, K. Aisaka, H. Kawaguchi, and T. Sakurai, "Frequency-Voltage Cooperative Power Reduction for Multi-tasking Multimedia Applications," International Symposium on Low-Power and High-Speed Chips (COOL Chips), Apr. 2003

#2003013

T. Sakurai, "Low Power Circuits and Techniques," IEEE Custom Integrated Circuits Conference, USA(San Jose), 28, May 2003

#2003019

T. Sakurai, "Reshaping EDA for Power," Design Automation Conference, USA(Anaheinm), 2, June 2003

#2003027

T.Someya,T. Sakurai, "Integration of Organic Filed-Effect Transistors and Rubbery Presssure Senso for Artificial Skin Applications," IEEE International Electron Devices Meeting, USA(Washington), pp.8.4.1-8.4.4, Sep. 12, 2003 (PDF)

#2003028

T. Sakurai, "For The LAST Time, Who Is Going To Solve The POWER Problem!," IEEE International Electron Devices Meeting, USA(Washington), 24, Sep. 12, 2003

#2003039

T. Sakurai, "(Invited)Perfective of Low Power Electronics," IEEE seminar on System on Chip: Design for Low power, France, Oct. 14, 2003

#2003040

T. Sakurai, "(Invited)System-on-a- Chip vs System-in-a-Package:design and interconnection issues," Advanced Metallization Conference(AMC)2003, Canada(Montreal), Oct. 21, 2003 (PDF)

#2003045

H. Im, T.Inukai, H.Gomyo, T.Hiramoto, T. Sakurai , "VTCMOS Characterisitics and Its Optimum Conditions Predicated By a Compact Analytical Model," IEEE Transaction‚“ on very large sacale intagration(VLSI) Systems, Vol.Vol.11, No.No.5, pp.755-761, Oct. 2003

#2003061

J. H. Choi, T. Sakurai, "Statistical Leakage Current Reduction by Self-Timed Cut-Off Scheme for High Leakage Environments," IEEE Custom Integrated Circuits Conference, USA(San Jose), 28.3, Sep. 24, 2003

#2003062

K. Min, K. Kanda, T. Sakurai,, "Row-by-row dynamic source-line voltage Control (RRDSV) Scheme for Two orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's ," IEEE/ACM International Symposium on Low Power Electronics and Design,, Seoul, pp.66-71, Aug. 25-27, 2003

H. Kawaguchi, G. Zhang, S. Lee, Y. Shin, and T. Sakurai, "A Controller LSI for Realizing Vdd-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System," IEICE Transactions on Electronics, Vol.E85-C, No.2, pp.263-271, Feb. 2002 (PDF)

#2002002

T. Sakurai, "Low-power and High-Speed V VLSI Design with Low Supple Voltage Through Cooperation between Levels(Invited)," IEEE International Symposium on Quality Electronic Design, San Jose, CA, USA, 4A, pp.445-450, Mar. 2002

#2002003

K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakura, "VTH-Hopping Scheme to Reduce Subthreshold Leakage for Low-Power Processors," IEEE Journal of Solid-State Circuits, Vol.37, No.3, pp.413-419, Mar. 2002 (PDF)

#2002006

T. Sakurai, "Low-Power LSI -Through cooperation among levels-," Germany-Japan Information Technology Forum, Birlinghoven/Windhagen, Germany, 2, Apr. 2002 (PDF)(PDF2)

#2002010

S. Hattori and T. Sakurai, "90% Write Power Saving SRAM Using Sense-Amplifying Memory Cell," Symposium on VLSI Circuits, Honolulu, HI, USA, 4.2, pp.46-47, June 2002 (PDF)

#2002012

Y. Shin and T. Sakurai, "Power Distribution Analysis of VLSI Interconnects Using Model Order Reduction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.21, No.6, pp.739-745, June 2002 (PDF)

#2002015

K. Nose and T. Sakurai, "Power-Conscious Interconnect Buffer Optimization with Improved Modeling of Driver MOSFET and Its Implications to Bulk and SOI CMOS Technology," International Symposium on Low Power Electronics and Design, Monterey, CA, USA, 1.4s, pp.24-29, Aug. 2002 (PDF)

#2002017

K. Kanda, T. Miyazaki, M. Kyeong Sik, H. Kawaguchi, and T. Sakurai, "Two Orders of Magnitude Leakage Power Reduction of Low Voltage SRAM's by Row-by-Row Dynamic VDD Control (RRDV) Scheme," IEEE ASIC/SOC conference, Rochester, NY, USA, FB2, pp.381-385, Sep. 2002

#2002018

T. Sakurai, "Minimizing Power Across Multiple Technology and Design Levels(Invited)," International Conference on Computer Aided Design, San Jose, CA, USA, 1B.1, pp.24-27, Nov. 2002

#2002022

S. S. Lee, S. J. Lee, and T. Sakurai, "Energy-Constrained VDD/VTH Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems," Journal of Circuits, Systems and Computers, Vol.11, No.6, pp.611-620, Dec. 2002 (PDF)

#2002023

H. Kawaguchi, K. Kanda, K. Nose, S. Hattori, D. D. Antono, D. Yamada, T. Miyazaki, K. Inagaki, T. Hiramoto, and T. Sakurai, "A 0.5-V, 400-MHz, VDD-Hopping Processor with Zero-VTH FD-SOI Technology," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 6.3, pp.108-109, Feb. 2003

#2002024

K. Kanda, D. D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, and T. Sakurai, "1.27-Gbps/pin, 3mW/pin Wireless Superconnect (WSC) Interface Scheme," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 10.7, pp.186-187, Feb. 2003

#2002025

K. S. Min and T. Sakurai, "Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 22.8, pp.400-401, Feb. 2003 (PDF)

#2002026

T. Sakurai, "Perspectives on Power-Aware Electronics (Plenary Talk, Invited)," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 1.2, pp.26-29, Feb. 2003

#2002031

Q. Liu, T. Sakurai, and T. Hiramoto, "Optimum Device Consideration for Standby Power Reduction Scheme Using Drain Induced Barrier Lowering (DIBL)," International Conference on Solid State Devices and Materials, Nagoya Congress Center, pp.258-259, Sep. 2002

#2002033

K. Aisaka, T. Aritsuka, S. Misaka, K. Toyama, K. Uchiyama, K. Ishibashi, H. Kawaguchi, and T. Sakurai, "Design rule for frequency-voltage cooperative power control and its application to an MPEG-4 Decoder," Symposium on VLSI Circuits, pp.216-217, June 2002 (PDF)

#2002034

J. Goodman, T. Sakurai, D. Buss, and T. Suga, "SOC (System-on-a-chip) versus SIP (System-in-a-package)," Symposium on VLSI Circuits, Panel discussion, pp.96, June 2002 (PDF)

T. Sakurai, "Low Power Design of Digital Circuits," International Symposium on Key Technologies for Future VLSI Systems, pp.1-5, Jan. 2001 (PDF)

#2001005

T. Sakurai, "Recent Topics for Realizing Low-Power, High-Speed VLSI's," International Symposium on Advanced CMOS Devices, pp.17-22, Oct. 31, 2001 (PDF)(PDF2)

#2001007

T. Sakurai, "Issues of Current LSI Technology and an Expectation for New System-Level Integration," International Conference on Solid State Devices and Materials, pp.36-37, Sep. 2001 (PDF)(PDF2)

#2001009

T. Sakurai, "Panel on Low-Voltage Design or the End of CMOS Scaling?," IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, Evening Session, Feb. 2002 (PDF)

#2001012

H. Im, T. Inukai, H. Gomyo, T. Hiramoto, and T. Sakurai, "VTCMOS Characteristics and Its Optimum Conditions Predicted by a Compact Analytical Model," International Symposium on Low Power Electronics and Design, pp.123-128, Aug. 2001 (PDF)(PDF2)

#2001013

T. Inukai, T. Hiramoto, and T. Sakurai, "Variable Threshold Voltage CMOS (VTCMOS) in Series Connected Circuits," International Symposium on Low Power Electronics and Design, pp.201-206, Aug. 2001 (PDF)(PDF2)

#2001014

Y. Shin and T. Sakrai, "Estimation of Power Distribution in VLSI Interconnects," International Symposium on Low Power Electronics and Design, pp.370-375, Aug. 2001 (PDF)

#2001015

M. Hirabayashi and T. Sakurai, "Design Methodology and Optimization Strategy for Dual-VTH Scheme using Commercially Available Tools," International Symposium on Low Power Electronics and Design, pp.283-286, Aug. 2001 (PDF)

#2001019

K. Nose, M. Hirabayashi, H. Kawaguchi, S. Lee, and T. Sakurai, "VTH-hopping scheme for 82% power saving in low-voltage processors," IEEE Custom Integrated Circuits Conference, pp.93-96, May 2001 (PDF)

#2001021

K. Nose and T. Sakurai, "Two schemes to reduce interconnect delay in bi-directional and uni-directional buses," Symposium on VLSI Circuits, pp.193-194, June 2001 (PDF)

#2001022

K. Nose and T. Sakurai, "Current sensing device for micro-IDDQ test," Electronics and Communications in Japan part 2, 84, 9, May 2001 (PDF)

#2001023

H. Kawaguchi, G. Zhang, S. Lee, and T. Sakurai, "An LSI for VDD-Hopping and MPEG4 System Based on the Chip," IEEE International Symposium on Circuit and Systems, pp.918-921, May 2001 (PDF)

#2001025

H. Kawaguchi, Y. Shin, and T. Sakurai, "Experimental Evaluation of Cooperative Voltage Scaling (CVS): A Case Study," IEEE Workshop on Power Management for Real-Time and Embedded Systems, pp.17-23, Feb. 2001 (PDF)

#2001037

K. Kanda, K. Nose, H. Kawaguchi, and T. Sakurai, "Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's," IEEE Journal of Solid-State Circuits, Vol.36, No.10, pp.1559-1564, Oct. 2001 (PDF)

#2001042

T. Sakurai, "Superconnect Technology (invited)," IEICE Transactions on Electronics, Vol.E84/C12, No., pp.1709-1716, June 2001 (PDF)

K. Nose, and T. Sakurai, "Analysis and Future Trend of Short-Circuit Power," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.19, No.9, pp.1023-1030, Sep. 2000 (PDF)

#2000007

H. Kawaguchi, K. Nose, and T. Sakurai, "A Super Cut-off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-by Current," IEEE Journal of Solid-State Circuits, Vol.35, No.10, pp.1498-1501, Oct. 2000 (PDF)

#2000008

Y. Shin, K. Choi, and T. Sakurai, "Power-Conscious Scheduling for Real-Time Embedded Systems Design," An International Journal of Custom-Chip Design, Simulation, and Testing, Vol., No., 2001 (PDF)

#2000010

T. Sakurai, "Design Challenges for 0.1um and Beyond," Asia and South Pacific Design Automation Conference, pp.553-558, Jan. 2000 (PDF)

#2000011

S. Lee, and T. Sakurai, "Run-Time Power Control Scheme Using Software Feedback Loop for Low-Power Real-Time Applications," Asia and South Pacific Design Automation Conference, pp.381-386, Jan. 2000 (PDF)

#2000012

N. D. Minh, and T. Sakurai, "Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies," Asia and South Pacific Design Automation Conference, pp.475-480, Jan. 2000 (PDF)

#2000013

K. Nose, and T. Sakurai, "Optimization of VDD and VTH for Low-Power and High-Speed Applications," Asia and South Pacific Design Automation Conference, pp.469-474, Jan. 2000 (PDF)

#2000014

T. Sakurai, "Low Power Design of Digital Circuits," International Symposium on Key Technologies for Future VLSI Systems, pp.1-5, Jan. 2000 (PDF)

#2000015

T. Sakurai, "Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control," IEEE International Symposium on Quality Electronic Design, pp.417-423, Mar. 2000 (PDF)

#2000016

T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, and T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration," IEEE Custom Integrated Circuits Conference, pp.409-412, May 2000 (PDF)

#2000017

S. Lee, and T. Sakurai, "Run-Time Voltage Hopping for Low-Power Real-Time Systems," Design Automation Conference, pp.806-809, June 2000 (PDF)

#2000018

K. Nose, S. Chae, and T. Sakurai, "Voltage Dependent Gate Capacitance and Its Impact in Estimating Power and Delay of CMOS Digital Circuits with Low Supply Voltage," International Symposium on Low Power Electronics and Design, pp.228-230, July 2000 (PDF)

#2000020

T. Sakurai, "Interconnection from Design Perspective," Advanced Metallization Conference, pp.53-58, Oct. 2000 (PDF)(PDF2)

#2000021

Y. Shin, K. Choi, and T. Sakurai, "Power Optimization of Real-Time Embedded Systems on Variable Speed Processors," International Conference on Computer Aided Design, pp.365-368, Nov. 2000 (PDF)

#2000022

T. Sakurai, "Super-connect," International Packaging Strategy Symposium, pp.19-26, Dec. 2000 (PDF)

#2000023

K. Kanda, N. D. Minh, H. Kawaguchi, and T. Sakurai, "Abnormal Leakage Suppression (ALS) Scheme for Low Standby Current SRAMs," IEEE International Solid-State Circuits Conference, pp.174-175, Feb. 2001 (PDF)

#2000024

Y. Shin, H. Kawaguchi, and T. Sakurai, "Cooperative Voltage Scaling (CVS) between OS and Applications for Low-Power Real-Time Systems," IEEE Custom Integrated Circuits Conference, pp.553-556, May 2001 (PDF)

#2000025

Y. Shin and T. Sakurai, "Coupling-Driven Bus Design for Low-Power Application-Specific Systems," Design Automation Conference, pp.750-753, June 2001 (PDF)

#2000026

Y. Shin and T. Sakurai, "Estimation of Power Distribution in VLSI Interconnects," International Symposium on Low Power Electronics and Design Accepted, Aug. 2001 (PDF)

#2000052

T. Sakurai, "VLSI design challenges in the forthcoming decade," In-Chip Systems, Feb. 2001

#2000053

T. Sakurai, "Software and Hardware Schemes for Achieving Low-Power," Microprocessor Design Symposium, Feb. 8, 2001

K. Nose and T. Sakurai, "Micro IDDQ Test using Lorenz Force MOSFET's," Symposium on VLSI circuits, pp.169-170, June 1999 (PDF)

#1999003

T. Sakurai, "Custom Circuit Techniques For High Performance And Low-Power Applications," IEEE Custom Integrated Circuits Conference, pp.277, May 1999

#1999008

T. Sakurai, "Panel on Hardware is King, Software is Queen: Has Hardware become a Second-Class Citizen to Software?," IEEE International Solid-State Circuits Conference, Panel discussion, pp.294-295, Feb. 1999

#1999009

T. Sakurai, "LSI design toward 2010 low-power technology," International Conference on VLSI and CAD, pp.325-334, Oct. 1999 (PDF)

#1999010

T. Sakurai, "Toward LSI's in the Year-From the Design Viewpoint," Symposium on Semiconductors and Integrated Circuits Technology, pp.95-105, June 1999

#1999011

T. Sakurai, "Low Voltage, High-speed VLSI Design," International Conference on Solid State Devices and Materials, pp.3-30, Sep. 1999

#1999033

T. Sakurai, "Design Impact of Positive Temperature Dependence of Drain Current in Sub 1V CMOS VLSI's," IEEE Custom Integrated Circuits Conference, May 1999

T. Sakurai, "Challenges for Low-Power and High-performance Chips," IEEE Design & Test of Computers, Vol., No.3, pp.119-124, Sep. 1998 (PDF)

#1998003

S. Ishiwata and T. Sakurai, "Future Directions of Media processors," IEICE Transactions on Electronics, Vol.E81-C, No.5, pp.629-635, May 1998 (PDF)

#1998004

H. Kawaguchi and T. Sakurai, "A Reduced Clock-Swing Flip-Flop(RCSFF)for 63% Power Reduction," IEEE Journal of Solid-State Circuits, Vol.33, No.5, pp.807-811, May 1998 (PDF)

#1998006

H. Kawaguchi, K. Nose, and T. Sakurai, "A COMS Scheme for 0.5v Supply Voltage with Pico-Ampere Standby Current," IEEE International Solid-State Circuits Conference, 12.4, pp.192-193, Feb. 1998 (PDF)

#1998007

H. Kawaguchi and T. Sakurai, "Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines," Asia and South Pacific Design Automation Conference, pp.35-43, Feb. 1998 (PDF)

#1998008

T. Sakurai, "Panel on How Will Media processors the Next Decade?," IEEE International Solid-State Circuits Conference, Panel discussion, pp.264-265, Feb. 1998

#1998009

T. Sakurai, "Audio and Video Digital Processing," IEEE Custom Integrated Circuits Conference, pp.167, May 1998

#1998010

H. Kawaguchi, Y. Itaka and T, Sakurai, "Dynamic Leakage Cut-off Scheme Low-Voltage SRAM's," Symposium on VLSI Circuits, pp.140-141, June 1998 (PDF)

#1998011

R. Allmon and T. Sakurai, "Panel on Visions of Computers in the year 2005," Symposium on VLSI Circuits, pp.69, June 1998 (PDF)

#1998012

H. Kawaguchi, K. Nose, and T. Sakurai, "A COMS Scheme for 0.5V Supply Voltage with Pico-Ampere Standby Current," International Workshop on Advanced LSIs, pp.45-49, July 1998 (PDF)

#1998013

S. Takeuchi and T. Sakurai, "A-Fine Grain, Current Mode Scheme for VLSI Proximity Search Engine," International Conference on Computer Design, pp.184-185, Oct. 1998 (PDF)

#1998014

K. Nose and T. Sakurai, "Integrated Current Sensing Device for Micro IDDQ Test," Asian Test Symposium, pp.323-326, Dec. 1998 (PDF)

#1998030

T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama, "Variable supply-voltage scheme for low-power high-speed CMOS digital design," IEEE Journal of Solid-State Circuits, Vol.33, No.3, pp.454-462, Mar. 1998 (PDF)

#1998031

W. Bidermann and T. Sakurai, "Foreword," IEEE Journal of Solid-State Circuits, Vol.33, No.5, pp.674-675, May 1998 (PDF)

#1998033

K. Nose and T. Sakurai, "Closed-Form Expressions for Short-Circuit Power Short-Channel CMOS Gates and Its Scaling Characteristics," International Technical Conference on Circuits/Systems, Computers and Communications, pp.1741-1744, July 1998 (PDF)

#1998040

T. Sakurai, "Moore's Law : when to break?," IEEE Symposia on VLSI Technology and Circuits, 1998

I. A. Young and T. Sakurai, "Editorial," IEEE Journal of Solid-State Circuits, Vol.32, No.5, pp.618-620, May 1997 (PDF)

#1997007

T. Kuroda and T. Sakurai, "Low-Power Circuit Design (invited)," Asia and South Pacific Design Automation Conference, 1, Jan. 1997

#1997008

T. Sakurai , T. Kuroda, "Low-Power Circuit Design for Multimedia LSI's (invited)," European Design and Test Conference, Mar. 1997

#1997009

K. Okada and T. Sakurai, "Audio and Video DSPs," IEEE Custom Integrated Circuits Conference, pp.223, May 1997

#1997010

T. Sakurai and T. Kuroda, "Low Voltage Technology and Circuits (invited)," Mead Microelectronics Conference, Lausanne, Switzerland, June 1997

#1997011

H. Kawaguchi and T. Sakurai, "A Reduced Clock-Swing Flip-Flop( RCSFF ) for 63% Clock Power Reduction," Symposium on VLSI Circuits, pp.97-98, June 1997 (PDF)

#1997012

T. Sakurai, H. Kawaguchi, and T. Kuroda, "Low-Power CMOS Design through VTH Control and Low-Swing Circuits (invited)," Digest International Symposiumon Low-Power Electronics and Design, pp.1-6, Sep. 1997 (PDF)

#1997013

H. Kawaguchi and T. Sakurai, "Noise Expressions for Capacitance-Coupled Distributed RC Lines," ACM / IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.270-279, Dec. 1997 (PDF)

#1997014

H. Kawaguchi and T. Sakurai, "Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines," Asia and South Pacific Design Automation Conference, pp.35-43, Feb. 1998

H. Hara, M. Matsui, G. Otomo, K. Seta, and T. Sakurai, "Special and Embedded Memory Macrocells for Low-Cost and Low-Power in MPEG Environment," IEICE Transactions on Electronics, Vol.E79-C, No.6, pp.750-756, June 1996 (PDF)

#1996002

A. Parameswar, H. Hara, and T. Sakurai, "A Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications," IEEE Journal of Solid-State Circuits, Vol.31, No.6, pp.804-809, June 1996 (PDF)

#1996003

T. Kuroda and T. Sakurai, "Threshold-Voltage Control Schemes through Substrate-Bias for Low-Power High-Speed CMOS LSI Designs (invited)," Journal of VLSI Signal Processors, Vol.13, No.2/3, pp.191-201, Aug. 1996

#1996004

T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9-V, 150-MHz 10-mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE Journal of Solid-State Circuits, Vol.31, No.11, pp.1770-1779, Nov. 1996 (PDF)

#1996005

T. Kuroda, T. Fujuta, T. Nagamatsu, S. Yoshioka, T. Sei, K. Matsumoto, Y. Hamura, T. Mori, M. Murota, M. Kakumu, and T. Sakurai, "A High-Speed Low-Power 0.3um CMOS Gate Array with Variable Threshold Voltage (VT) Scheme," IEEE Custom Integrated Circuits Conference, pp.53-56, May 1996

#1996006

T. Sakurai, "Video, Image and Speech Digital Signal Processing," IEEE Custom Integrated Circuits Conference, pp.349, May 1996

#1996007

K. Suzuki, T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, F. Sano, M. Norishima, M. Murota, M. Kato, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage (VT) Scheme," 4th International Workshop on Advanced LSI's, pp.150-158, July 1996

#1996008

T. Sakurai and T. Kuroda, "Achieving Low-Power Through Control of Threshold Voltage (invited)," XXXVth General Assembly of the International Union of Radio Science (URSI) Abstracts, pp.168, Aug. 1996

#1996009

T. Kuroda, T. Fujita, S. Mita, T. Mori, K. Matsuo, M. Kakumu, and T. Sakurai, "Substrate Noise Influence on Circuit Performance in Variable Threshold-Voltage Scheme," International Symposium on Low Power Electronics and Design, pp.309-312, Oct. 1996 (PDF)

#1996010

T. Sakurai and T. Kuroda, "Tutorial on Low-Power Design Methodology (invited)," Proc. of the Synthesis and System Integration of Mixed Technologies (SASIMI), pp.3-10, Nov. 1996

#1996012

T. Sakurai and T. Kuroda, "Low-Power Circuit Design for Multimedia LSI's," European Design and Test Conference, Mar. 1997

#1996013

T. Sakurai and T. Kuroda, "Low-Voltage Technology and Circuits (invited)," Mead Microelectronics Conference, Mar. 1997

#1996015

T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kobayashi, T. Takayanagi, K. Nogami, F. Hatori, N. Hatanaka, M. Takahashi, M. Ichida, S. Kobayashi, T. Higashi, M. Klein, J. Thomson, R. Carpenter, R. Donthi, D. Renfrow, J. Zheng, L. Tinkey, B. Maness, J. Battle, S. Purcell, and T. Sakurai, "350MHz Time-Multiplexed 8-Port SRAM and Word-Size Variable Multiplier for Multimedia DSP," IEEE International Solid-State Circuits Conference, 9.4, pp.150-151, Feb. 1996 (PDF)

#1996016

Y. Unekawa, K. Fkuda, K. Sakue, T. Nakao, S. Yoshioka, T. Nagamatsu, H. Nakakita, Y. Kaneko, M. Motomiya, Y. Ohba, K. Ise, M. Ono, K. Fujiwara, Y. Miyazawa, T. Kuroda, Y. Kamitani, T. Sakurai, and A. Kanuma, "A 5Gb/s 8 x 8 ATM Switch Element CMOS LSI Supp. Rting Five Quality-Of-Service Classes with 200MHz LVDS Interface," IEEE International Solid-State Circuits Conference, 7.3, pp.118-119, Feb. 1996 (PDF)

#1996017

T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. yoshioka, F. Sano, M. Norishima, M. Murota, M. Kato, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9V 150MHz 10mW 4mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme," IEEE International Solid-State Circuits Conference, 10.3, pp.166-167, Feb. 1996 (PDF)

K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, "50% Active Power Saving without Speed Degradation Using Standby Power Reduction (SPR) Circuit," IEEE International Solid-State Circuits Conference, 19.4, pp.318-319, Feb. 1995 (PDF)

#1995003

T. Kuroda and T. Sakurai, "Overview of Low-Power ULSI Circuit Techniques(invited)," IEICE Transactions on Electronics, Vol.E78-C, No.4, pp.334-344, Apr. 1995 (PDF)

#1995006

G. Otomo, H. Hara, T. Oto, K. Seta, K. Kitagaki, S, Ishiwata, S. Michinaka, T. Shimazawa, M. Matsui, T. Demura, M. Koyama, Y. Watanabe, F. Sano, A. Chiba, K. Matsuda, and T. Sakurai, "Special Memories and Embedded Memories in MPEG Environments(invited)," IEEE Custom Integrated Circuits Conference, 8.1, May 1995

#1995008

T. Sakurai, "Tutorial on Low-Power Circuit Design Methodology(invited)," Asia and South Pacific Design Automation Conference, Aug. 1995

#1995010

T. Sakurai, "Low-Power Circuit Design for Multimedia(invited)," Proc. of the International Conference on VLSI and CAD (ICVC), pp.37-42, Oct. 1995

Y. Unekawa, T. Kobayashi, T. Shirotori, Y. Fujimoto, T. Shimazawa, K. Nogami, T. Nakao, K. Sawada, M. Matsui, T. Sakurai, M. K.Tang, and B. Huffman, "A 110-MHz/1-Mb Synchronous TagRAM," IEEE Journal of Solid-State Circuits, Vol.29, No.4, pp.403-410, Apr. 1994 (PDF)

#1994002

M. Matsui, H. Hara, K. Seta, Y. Uetani, L. Kim, T. Nagamatsu, T. Shimazawa, S. Mita, G. Otomo, T. Oto, Y. Watanabe, F. Sano, A. Chiba, K. Matsuda, and T. Sakurai, "200MHz Video Compression Macrocells Using Low-Swing Differential Logic," IEEE International Solid-State Circuits Conference, 4.6, pp.76-77, Feb. 1994 (PDF)

#1994003

T. Demura, T. Oto, K. Kitagaki, S. Ishiwata, G. Otomo, S. Michinaka, N. Goto, M. Matsui, H. Hara, T. Nagamatsu, K. Seta, T. Shimazawa, K. Maeguchi, T. Odaka, Y. Uetani, T. Oku, T. Yamakage, and T. Sakurai, "A Single-Ship MPEG2 Decoder LSI," IEEE International Solid-State Circuits Conference, 4.4, pp.72-73, Feb. 1994 (PDF)

#1994004

A. Parameswar, H. Hara, and T. Sakurai, "A High-Speed, Low-Power, Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit for Multimedia Applications," IEEE Custom Integrated Circuits Conference, pp.278-281, May 1, 1994

#1994005

T. Takayanagi, K. Sawada, T. Sakurai, Y. Parameshwar, S. Tanaka, N. Ikumi, M. Nagamatsu, Y. Kondo, K. Minagawa, J. Brennan, P. Hsu, P. Rodman, J. Bratt, J. Scanlon, M. Tang, C. Joshi, and M. Nofal, "Embedded Memory Design for a Four Issue Superscaler RISC Microprocessor(invited)," IEEE Custom Integrated Circuits Conference, pp.585-590, May 1994

#1994006

T. Kobayashi, and T. Sakurai, "Self-Adjusting Threshold-Voltage Scheme (SATS) for Low-Voltage High-Speed Operation," IEEE Custom Integrated Circuits Conference, pp.271-274, May 1994

#1994009

M. Matsui, H. Hara, Y. Uetani, L. Kim, T. Nagamatsu, Y. Watanabe, A. Chiba, K. Matsuda, and T. Sakurai, "A 200MHz 13mm2 2-D DCT Macrocell Using Sense-Amplifying Pipeline Flip-Flop Scheme," IEEE Journal of Solid-State Circuits, Vol.29, No.12, pp.1482-1490, Dec. 1994 (PDF)

#1994010

I. Young and T. Sakurai, "Future high performance microprocessor implementation tradeoffs," Symposium on VLSI Circuits, Panel discussion, pp.49, June 1994 (PDF)

Y. Unekawa, T. Kobayashi, T. Shirotori, Y. Fujimoto, T. Shimazawa, K. Nogami, T. Nakao, K. Sawada, M. Matsui, T. Sakurai, M. K.Tang, and B. Huffman, "A 110MHz/1Mbit Synchronous TagRAM," Symposium on VLSI Circuits, pp.15-16, 1993 (PDF)

#1993002

F. Hatori, T. Sakurai, K. Nogami, K. Sawada, M. Takahashi, M. Ichida, M. Uchida, I. Yoshii, Y. Kawahara, Y. Hibi, Y. Saeki, H. Muroga, A. Tanaka, and K. Kanzaki, "Introducing Redundancy in Field Programmable Gate Arrays," IEEE Custom Integrated Circuits Conference, pp.7.1.1-7.1.4, May 1993

#1993003

T. Sakurai, "High Speed / High-Density Logic Circuit Design(invited)," International Symposium on VLSI Technology, Systems, and Applications, Taiwan, pp.222-226, May 12-14, 1993

#1993004

T. Sakurai, "High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage(invited)," IEEE International Symposium on Circuit and Systems, Chicago, pp.1487-1490, May 1993 (PDF)

#1993005

T. Sakurai, "Closed-Form Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI's," IEEE Transactions on Electron Devices, Vol.40, No.1, pp.118-124, Jan. 1993 (PDF)

#1993006

T. Sakurai and A. El Gamal, "Multi-million gate ASIC's," Symposium on VLSI Circuits, Panel discussion, pp.95, May 1993 (PDF)

T. Sakurai, "A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization," IEEE Journal of Solid-State Circuits, Vol.27, No.7, pp.1014-1019, July 1992 (PDF)

#1992002

H. Hara, T. Sakurai, T. Nagamatsu, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, K. Matsuda, Y. Watanabe, F. Sano, and A. Chiba, "0.5-um 3.3-V BiCMOS Standard Cells with 32-kilobyte Cache and Ten-Port Register File," IEEE Journal of Solid-State Circuits, Vol.27, No.11, pp.1579-1584, Nov. 1992 (PDF)

#1992003

T. Sakurai, "Panel on High Speed I/O," IEEE International Solid-State Circuits Conference, Panel discussion, pp.188, Feb. 1992

#1992004

T. Sakurai, B. Lin and A. R. Newton, "Fast Simulated Diffusion: An Optimization Algorithm for Multi-minimum Problems and Its Application to MOSFET Model Parameter Extraction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.11, No.2, pp.228-234, Feb. 1992 (PDF)

#1992005

H. Hara and T. Sakurai et al., "0.5um BiCMOS Standard-Cell Macros Including 0.5W 3ns Register File and 0.6W 5ns 32kB Cache," International Solid-State Circuits Conference, pp.46-47, Feb. 1992 (PDF)

#1992008

T. Mori, T. Sakurai et al., "0.5um BiCMOS ASIC Family," IEEE Custom Integrated Circuits Conference, Session2 New Products - High Performance Devices and Test Methodologies, May 1992

#1992010

M. Takahashi, T. Sakurai, K. Sawada, K. Nogami, and M. Ichida, "3.3V - 5V Compatible I/O Circuit without Thick Gate Oxide," IEEE Custom Integrated Circuits Conference, pp.23.3.1-23.3.4, May 1992

#1992011

T. Sakurai, "A Review on Low-Voltage BiCMOS Circuits and a BiCMOS vs. CMOS Speed Comparison," 35th Midwest Symposium on Circuits and Systems, Washington DC, pp.564-567, Aug. 1992

T. Sakurai and A. R. Newton, "Delay Analysis of Series-Connected MOSFET Circuits," IEEE Journal of Solid-State Circuits, Vol.26, No.2, pp.122-131, Feb. 1991 (PDF)

#1991002

T. Sakurai, S. Kobayashi, and M. Noda, "Simple Expressions for Interconnection Delay, Coupling and Crosstalk in VLSI's," IEEE International Symposium on Circuit and Systems, pp.2375-2378, June 1991

#1991003

T. Sakurai and A. R. Newton, "A Simple Short-Channel MOSFET Model and Its Application to Delay Analysis of Inverters and Series-Connected MOSFET's," IEEE International Symposium on Circuit and Systems, TUAM-3-7, May 1990

#1991004

T. Sakurai and A. R. Newton, "A Simple MOSFET Model for Circuit Analysis," IEEE Transactions on Electron Devices, Vol.38, No.4, pp.887-894, Apr. 1991 (PDF)

#1991005

T. Sakurai, "A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization," IEEE European Solid-State Circuits Conference, pp.129-132, Sep. 1991

#1991006

T. Nagamatsu, T. Sakurai, H. Hara, S. Kobayashi, K. Seta, M. Noda, M. Uchida, Y. Watanabe, and F. Sano, "A 1.9ns BiCMOS CAM Macro with Double Match Line Architecture," IEEE Custom Integrated Circuits Conference, pp.14.3.1-14.3.4, May 1991

#1991007

H. Hara, T. Sakurai, M. Noda, T. Nagamatsu, S. Kobayashi, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, K. Maeguchi, Y. Watanabe, and F. Sano, "0.5um 2M-Transistor BiPNMOS Channelless Gate Array," IEEE International Solid-State Circuits Conference, 9.1, pp.148-149, Feb. 1991 (PDF)

#1991008

T. Sakurai, "Panel on Silicon Integrated Systems Beyond Half Micron," IEEE International Solid-State Circuits Conference, Panel discussion, pp.197, Feb. 1991

#1991009

T. Sakurai, M. Ichida and A. R. Newton, "Fast Simulated Diffusion: An Optimization Algorithm for Multi-Minimum Problems and Its Application to MOSFET Model Parameter Extraction," IEEE Custom Integrated Circuits Conference, pp.8.8.1-8.8.4, May 1991

#1991011

H. Hara, T. Sakurai, M. Noda, T. Nagamatsu, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, and Y. Watanabe, "0.5-um 2M-Transistor BiPNMOS Channelless Gate Array," IEEE Journal of Solid-State Circuits, Vol.26, No.11, pp.1615-1620, Nov. 1991 (PDF)

T. Sakurai and A. R. Newton, "Alpha-Power Law MOSFET Model and Its Application to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid-State Circuits, Vol.25, No.2, pp.584-594, Apr. 1990 (PDF)

#1990005

T. Sakurai, "High-Speed Circuit Design," IEEE Custom Integrated Circuits Conference, Educational Session E2.1, May 1990

#1990006

K. Nogami, T. Sakurai, K. Sawada, K. Sakaue, Y. Miyazawa, S. Tanaka, Y. Hiruta, K. Katoh, T. Takayanagi, T. Shirotori, Y. Itoh, M. Uchida, and T. Iizuka, "A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC," IEEE Journal of Solid-State Circuits, Vol.25, No.1, pp.100-108, Feb. 1990 (PDF)

K. Nogami, T. Sakurai, K. Sawada, K. Sakaue, Y. Miyazawa, S. Tanaka, Y. Hiruta, K. Katoh, T. Takayanagi, T. Shirotori, Y. Itoh, M. Uchida, and T. Iizuka, "Circuit design of a 9ns-HIT-delay 32K byte cache macro," Symposium on VLSI Circuits, pp.45-46, May 1989 (PDF)

T. Sakurai, "Optimization of CMOS Arbiter and Synchronizer with Sub-micron MOSFETs," IEEE Journal of Solid-State Circuits, Vol.23, No.4, pp.901-906, Aug. 1988 (PDF)

#1988002

K. Sawada, T. Sakurai, K. Nogami, T. Iizuka, Y. Uchino, Y. Tanaka, T. Kobayashi, K. Kawagai, Y. Shiotari, Y. Itabashi, and S. Kohyama, "A 72K CMOS Channelless Gate Array with Embedded 1Mbit Dynamic RAM," IEEE Custom Integrated Circuits Conference, pp.20.3.1-20.3.4, May 1988 (PDF)

#1988003

T. Sakurai, K. Nogami, K. Sawada, and T. Iizuka, "Transparent-Refresh DRAM (TReD) Using Dual-Port DRAM Cell," IEEE Custom Integrated Circuits Conference, pp.4.3.1-4.3.4, May 1988 (PDF)

#1988004

T. Sakurai, K. Nogami, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maeguchi, K. Kobayashi, T. Ando, Y. Hayakashi, A. Miyoshi, and K. Sato, "A Circuit Design of 32KByte Integrated Cache Memory," Symposium on VLSI Circuits, pp.45-46, Aug. 1988 (PDF)

#1988005

K. Nogami, T. Sakurai, K. Sawada, T. Shirotori, T. Takayanagi, T. Iizuka, T. Maeda, J. Matsunaga, H. Fuji, K. Maeguchi, K. Kobayashi, T. Ando, Y. Hayakashi, A. Miyoshi, and K. Sato, "Architecture and Design Methodology of 32KByte Integrated Cache Memory," IEEE European Solid-State Circuits Conference, Sep. 1988

#1988010

T. Iizuka, T. Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, and T. Miyoshi, "Large Memory Embedded ASICs (Invited)," International Conference on Computer Design, Dec. 1988

#1988011

T. Sakurai, "CMOS Inverter Delay and Other Analytical Formulas Using a-Power Law MOS Model," International Conference on Computer Aided Design, pp.74-77, Nov. 1988 (PDF)

T. Sakurai, "Panel on Digital ICs with Embedded Memory," IEEE International Solid-State Circuits Conference, Panel discussion, pp.239, Feb. 1987

#1987002

T. Sakurai, K. Sawada, K. Nogami, T. Wada, K. Sato, M. Kakumu, S. Morita, M. Kinugawa, T. Asami, K. Narita, J. Matsunage, A. Higuchi, and T. Iizuka, "A 36ns 1Mbit Pseudo SRAM with VSRAM mode," Symposium on VLSI Circuits, pp.45-46, May 1987 (PDF)

#1987003

K. Nogami, K. Sawada, M. Kinugawa, and T. Sakurai, "VLSI Circuit Reliability under AC Hot-Carrier Stress," Symposium on VLSI Circuits, pp.13-14, May 1987 (PDF)

#1987008

K. Sawada, T. Sakurai, K. Nogami, K. Sato, T. Shirotori, M. Kakumu, S. Morita, M. Kinugawa, T. Asami, K. Narita, J. Matsunaga, A. Higuchi, and T. Iizuka, "A 30-uA Data-Retention Pseudostatic RAM with Virtually Static RAM Mode," IEEE Journal of Solid-State Circuits, Vol.23, No.1, pp.12-19, Feb. 1988 (PDF)

#1987012

D. R.Asdsen, J. J.Barnes, B. Barton, S. Chan, D. Draper, P. A.Reed, T. Sakurai, "Digital ICs with Embedded Memory," IEEE International Solid-State Circuits Conference, International discussion 6, Feb. 26, 1987 (PDF)

T. Sakurai, K. Sawada, K. Nogami, T. Wada, M. Isobe, M. Kakumu, S. Morita, M. Yokogawa, M. Kinugawa, T. Asami, K. Hashimoto, J. Matsunage, H. Nozawa, and T. Iizuka, "A 1Mb Virtually SRAM," IEEE International Solid-State Circuits Conference, pp.252-253, Feb. 1986 (PDF)

#1986002

T. Sakurai, K. Nogami, M. Kakumu, and T. Iizuka, "Hot-Carrier Generation in Submicrometer VLSI Environment," IEEE Journal of Solid-State Circuits, Vol.21, No.1, pp.187-192, Feb. 1986 (PDF)

#1986003

K. Nogami, T. Sakurai, K. Sawada, T. Wada, M. Isobe, M. Kakumu, S. Morita, M. Yokogawa, M. Kinugawa, T. Asami, K. Hashimoto, J. Matsunage, H. Nozawa, and T. Iizuka, "A 1Mb Virtually Static RAM," IEEE Journal of Solid-State Circuits, Vol.21, No.5, pp.662-669, Oct. 1986 (PDF)

#1986004

K. Sawada, T. Sakurai, K. Nogami, T. Wada, M. Isobe, and T. Iizuka, "Self-Aligned Refresh Scheme for VLSI Intelligent Dynamic RAMs," Symposium on VLSI Technology, pp.85-86, May 1986 (PDF)

T. Sakurai, M. Kakumu, and T. Iizuka, "Hot-Carrier Suppressed VLSI with Submicron Geometry," IEEE International Solid-State Circuits Conference, pp.272-273, Feb. 1985 (PDF)

#1985003

T. Sakurai and T. Iizuka, "Gate Electrode RC Delay Effects in VLSI's," IEEE Journal of Solid-State Circuits, Vol.20, No.1, pp.290-294, Feb. 1985 (PDF)

#1985004

T. Sakurai and T. Iizuka, "Gate Electrode RC Delay Effects in VLSI's," IEEE Transactions on Electron Devices, Vol.32, No.2, pp.370-374, Feb. 1985 (PDF)

#1985005

K. Sawada, T. Sakurai, and T. Iizuka, "On-Chip Battery Backup Circuit for VLSI Static RAMs," International Conference on Solid State Devices and Materials, pp.49-52, 1985

#1985008

K. Hashimoto, Y. Nagakubo, S. Yokogawa, M. Kakumu, M. Kinugawa, K. Sawada, T. Sakurai, M. Isobe, J. Matsunage, and T. Iizuka, "Deep Trench Well Isolation for 256Kbit CMOS Static RAM," Symposium on VLSI Technology, pp.94-95, May 1985

T. Sakurai, K. Sawada, and T. Iizuka, "VLSI-oriented Voltage Down Conversion Circuits with Sub-Main Configuration," Late News Abstract of the International Conference on Solid State Devices & Materials, LC-12-7, pp.74, 1984 (PDF)

#1984008

M. Isobe, J. Matsunaga, T. Sakurai, T. Ohtani, K. Sawada, H. Nozawa, T. Iizuka, and S. Kohyama, "A 46ns 256Kbit CMOS SRAM," IEEE International Solid-State Circuits Conference, pp.214-215, Feb. 1984 (PDF)

#1984009

T. Sakurai, J. Matsunaga, M. Isobe, T. Ohtani, K. Sawada, A. Aono, H. Nozawa, T. Iizuka, and S. Kohyama, "A Low Power 46 ns 256 kbit CMOS SRAM with Dynamic Double Word Line," IEEE Journal of Solid-State Circuits, Vol.19, No.5, pp.578-585, Oct. 1984 (PDF)

T. Sakurai and K. Tamaru, "Simple Formulas for Two- and Three-Dimensional Capacitances," IEEE Transactions on Electron Devices, Vol.30, No.2, pp.183-185, Feb. 1983 (PDF)

#1983002

T. Sakurai, "Approximation of Wiring Delay in MOSFET LSI," IEEE Journal of Solid-State Circuits, Vol.18, No.4, pp.418-425, Aug. 1983 (PDF)

#1983003

T. Sakurai and T. Iizuka, "Double Word Line and Bit Line Structure for VLSI RAMs -- Reduction of Word Line Delay and Bit Line Delay," International Conference on Solid State Devices and Materials, Tokyo, (A-7-6), pp.269-272, 1983 (PDF)

#1983004

T. Iizuka and T. Sakurai, "CR Isolated Cell for Soft Error Prevention -- Static RAM Application," Symposium on VLSI Technology, Hawaii, pp.70-71, May 1983 (PDF)

T. Sakurai and T. Sugano, "Gap States of Crystalline Silicon and Amorphous SiO2 System," Conference on Physics of MOS Insulators, North Carolina, June 1980

#1980006

T. Sakurai and T. Sugano, "Theory of Continuously Distributed Trap States at Si-SiO2 Interfaces," Journal of Applied Physics, Vol.52(4), No., pp.2889-1296, Apr. 1981 (PDF)