Professor Takayasu Sakurai

Takayasu Sakurai (IEEE S'77-M'78-SM'01-F'03) received the Ph.D. degree in EE from the University of Tokyo in 1981. In 1981 he joined Toshiba Corporation, where he designed CMOS DRAM, SRAM, RISC processors, DSPs, and SoC Solutions. He has worked extensively on interconnect delay and capacitance modeling known as Sakurai model and alpha power-law MOS model. From 1988 through 1990, he was a visiting researcher at the University of California Berkeley, where he conducted research in the field of VLSI CAD. From 1996, he has been a professor at the University of Tokyo, working on low-power high-speed VLSI, memory design, interconnects, ubiquitous electronics, organic IC's and large-area electronics. He has published more than 600 technical publications including 100 invited presentations and several books and filed more than 200 patents. He is the executive committee chair for VLSI Symposia and a steering committee chair for the IEEE A-SSCC. He served as a conference chair for the Symp. on VLSI Circuits, and ICICDT, a vice chair for ASPDAC, a TPC chair for the A-SSCC, and VLSI symp., an executive committee member for ISLPED and a program committee member for ISSCC, CICC, A-SSCC, DAC, ESSCIRC, ICCAD, ISLPED, and other international conferences. He is a recipient of 2010 IEEE Donald O. Pederson Award in Solid-State Circuits, 2009 and 2010 IEEE Paul Rappaport award, 2010 IEICE Electronics Society award, 2009 IEICE achievement award, 2005 IEEE ICICDT award, 2004 IEEE Takuo Sugano award and 2005 P&I patent of the year award and four product awards. He delivered keynote speech at more than 50 conferences including ISSCC, ESSCIRC and ISLPED. He was an elected AdCom member for the IEEE Solid-State Circuits Society and an IEEE CAS and SSCS distinguished lecturer. He is also a domain research supervisor for nano-electronics area in Japan Science and Technology Agency. He is an IEICE Fellow and IEEE Fellow.

His publication list is here
His favorite poem

Prof. Takayasu Sakurai's japanese page


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